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MCP4142T-103E/ML 数据表(PDF) 12 Page - Microchip Technology

部件名 MCP4142T-103E/ML
功能描述  7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory
PDF  88 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP4142T-103E/ML 数据表(HTML) 12 Page - Microchip Technology

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MCP414X/416X/424X/426X
DS22059B-page 12
© 2008 Microchip Technology Inc.
FIGURE 1-2:
SPI Timing Waveform (Mode = 00).
TABLE 1-2:
SPI REQUIREMENTS (MODE = 00)
#
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—10
MHz VDD = 2.7V to 5.5V
—1
MHz VDD = 1.8V to 2.7V
70
CS Active (VIL or VIHH) to SCK↑ input
TcsA2scH
60
—
ns
71
SCK input high time
TscH
45
—
ns
VDD = 2.7V to 5.5V
500
—
ns
VDD = 1.8V to 2.7V
72
SCK input low time
TscL
45
—
ns
VDD = 2.7V to 5.5V
500
—
ns
VDD = 1.8V to 2.7V
73
Setup time of SDI input to SCK
↑ edge
TDIV2scH
10
—
ns
74
Hold time of SDI input from SCK
↑ edge
TscH2DIL20
—
ns
77
CS Inactive (VIH) to SDO output hi-impedance
TcsH2DOZ—
50
ns
Note 1
80
SDO data output valid after SCK
↓ edge
TscL2DOV—
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
82
SDO data output valid after
CS Active (VIL or VIHH)
TssL2doV
—
70
ns
83
CS Inactive (VIH) after SCK↓ edge
TscH2csI
100
—
ns
VDD = 2.7V to 5.5V
1ms
VDD = 1.8V to 2.7V
84
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
—
ns
Note 1:
This specification by design.
CS
SCK
SDO
SDI
70
71
72
82
SDI
74
75, 76
MSb
BIT6 - - - - - -1
LSb
77
MSb IN
BIT6 - - - -1
LSb IN
80
83
84
73
VIH
VIL
VIHH
VIH



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