MCP4142T-103ESLASHMS datasheet(54/88 Pages) MICROCHIP

54 / 88 page

MCP414X/416X/424X/426X

DS22059B-page 54

7.7.2

CONTINUOUS INCREMENTS

Continuous Increments are possible only when writing

to the volatile memory registers (address 00h, and

01h).

Figure 7-7 shows a Continuous Increment sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing an continuous Increment commands,

the selected wiper will be altered from n to n+1 for each

Increment command received. The wiper value will

increment up to 100h on 8-bit devices and 80h on 7-bit

devices. After the wiper value has reached Full-Scale

(8-bit =100h, 7-bit =80h), the wiper value will not be

incremented further. If the Wiper register has a value

between 101h and 1FFh, the Increment command is

disabled.

Increment commands can be sent repeatedly without

raising CS until a desired condition is met. The value in

the Volatile Wiper register can be read using a Read

Command

and

written

the

corresponding

Non-Volatile Wiper EEPROM using a Write Command.

When executing a continuous command string, The

Increment command can be followed by any other valid

command.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is incremented to the desired position,

the CS pin should be forced to VIH to ensure that

unexpected transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to VIH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

FIGURE 7-7:

Continuous Increment Command - SDI and SDO States.

XXA

X X

111111 1* 11

11111 1* 1111111 1* 1 Note 1, 2

111111

0 Note 3, 4

111111111

11111

0 Note 3, 4

111111111

1111111111111

0 Note 3, 4

(INCR COMMAND (n+1) )

(INCR COMMAND (n+2) )

(INCR COMMAND (n+3) )

SDI

SDO

COMMAND BYTE

Note 1:

Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

Valid Address/Command combination.

Invalid Address/Command combination.

If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

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