24LC32AF-ISLASHMS datasheet(11/30 Pages) MICROCHIP

11 / 30 page

DS22184A-page 11

24AA32AF/24LC32AF

8.0

READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

control byte is set to ‘1’. There are three basic types of

read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24XX32AF contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX32AF issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer, but does generate a Stop condition and the

24XX32AF discontinues transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must

first be set. This is accomplished by sending the word

address to the 24XX32AF as part of a write operation

(R/W bit set to ‘0’). Once the word address is sent, the

master generates a Start condition following the

acknowledge. This terminates the write operation, but

not before the internal Address Pointer is set. The

master issues the control byte again, but with the R/W

bit set to a ‘1’. The 24XX32AF will then issue an

acknowledge and transmit the 8-bit data word. The

master will not acknowledge the transfer, but does

generate

Stop

condition

which

causes

the

24XX32AF to discontinue transmission (Figure 8-2).

After a random Read command, the internal address

counter will point to the address location following the

one that was just read.

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read, except that once the 24XX32AF trans-

mits the first data byte, the master issues an acknowl-

edge as opposed to the Stop condition used in a

random read. This acknowledge directs the 24XX32AF

to transmit the next sequentially addressed 8-bit word

(Figure 8-3). Following the final byte transmitted to the

master, the master will NOT generate an acknowledge,

but will generate a Stop condition. To provide sequen-

tial reads, the 24XX32AF contains an internal Address

Pointer which is incremented by ‘1’ upon completion of

each operation. This Address Pointer allows the entire

memory contents to be serially read during one

operation. The internal Address Pointer will automati-

cally roll over from address FFF to address 000 if the

master acknowledges the byte received from the array

address FFF.

FIGURE 8-1:

CURRENT ADDRESS READ

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data (n)

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