MPC5604B datasheet(14/72 Pages) FREESCALE

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MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4

Electrical characteristics

Freescale Semiconductor

5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,

device is reset.

6 Guaranteed by device validation

Table 8. Recommended operating conditions (5.0 V)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VSS

SR Digital ground on VSS_HV pins

—

VDD

SR Voltage on VDD_HV pins with respect to

ground (VSS)

—

4.5

5.5

Voltage drop2

3.0

5.5

VSS_LV

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground

(VSS)

—

VSS−0.1 VSS+0.1

VDD_BV

SR Voltage on VDD_BV pin (regulator

supply) with respect to ground (VSS)

—

4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD

VDD−0.1 VDD+0.1

VSS_ADC

SR Voltage on VSS_HV_ADC (ADC

reference) pin with respect to ground

(VSS

—

VSS−0.1 VSS+0.1

VDD_ADC

SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (VSS)

—

4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD

VDD−0.1 VDD+0.1

VIN

SR Voltage on any GPIO pin with respect to

ground (VSS)

—

VSS−0.1

—

Relative to VDD

—

VDD+0.1

IINJPAD

SR Injected input current on any pin during

overload condition

—

−5

IINJSUM

SR Absolute sum of all injected input

currents during overload condition

—

−50

TVDD

SR VDD slope to ensure correct power up

—

0.25

V/µs

—

V/s

TA C-Grade Part SR Ambient temperature under bias

fCPU < 64 MHz

−40

°C

TJ C-Grade Part SR Junction temperature under bias

—

−40

110

TA V-Grade Part

SR Ambient temperature under bias

fCPU < 64 MHz

−40

105

TJ V-Grade Part

SR Junction temperature under bias

—

−40

130

TA M-Grade Part SR Ambient temperature under bias

fCPU < 60 MHz

−40

125

TJ M-Grade Part SR Junction temperature under bias

—

−40

150

1 100 nF capacitance needs to be provided between each V

DD/VSS pair.

2 Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog

electrical characteristics will not be guaranteed to stay within the stated limits.

3 330 nF capacitance needs to be provided between each V

DD_LV/VSS_LV supply pair.

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