SC9S12HY64J0CLLR datasheet(50/790 Pages) FREESCALE

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Device Overview MC9S12HY/HA-Family

MC9S12HY/HA-Family Reference Manual, Rev. 1.04

Freescale Semiconductor

1.11.3.4

Memory

The RAM arrays are not initialized out of reset.

1.12

COP Conﬁguration

The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are

loaded from the Flash register FOPT. See Table 1-13 and Table 1-14 for coding. The FOPT register is

loaded from the Flash conﬁguration ﬁeld byte at global address 0x3_FF0E during the reset sequence.

1.13

ATD External Trigger Input Connection

The ATD module includes external trigger inputs ETRIG[3:0]. The external trigger allows the user to

synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the external

trigger inputs.

Table 1-13. Initial COP Rate Conﬁguration

NV[2:0] in

FOPT Register

CR[2:0] in

COPCTL Register

000

111

001

110

010

101

011

100

011

101

010

110

001

111

000

Table 1-14. Initial WCOP Conﬁguration

NV[3] in

FOPT Register

WCOP in

COPCTL Register

Table 1-15. ATD External Trigger Sources

External Trigger

Input

Connectivity

ETRIG0

PP1(1)

1. When LCD segment output driver is enabled on PP1/PP3, the ATD

external trigger function will be unavailable

ETRIG1

PP31

ETRIG2

TIM0 Channel output 2(2)

2. Independent of the TIM0OCPD3/2 bit setting

ETRIG3

TIM0 Channel output 32

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