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SC9S12HY64J0CLLR 数据表(PDF) 57 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLLR 数据表(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 790 page ![]() Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 57 S PS7 SS I/O SS of SPI GPIO SDA I/O SDA of IIC PWM3 O PWM channel 3, mappable through software GPIO I/O General purpose PS6 KWS[6] I Key Wakeup SCK I/O SCK of SPI PWM2 O PWM channel 2, mappable through software GPIO I/O General purpose PS5 KWS[5] I Key Wakeup MOSI I/O MOSI of SPI PWM1 O PWM channel 1, mappable through software GPIO I/O General purpose PS4 MISO I/O MISO of SPI SCL I/O SCL of IIC PWM0 O PWM channel 0, mappable through software GPIO I/O General purpose PS3 TXCAN O TX of CAN GPIO I/O General purpose PS2 RXCAN I RX of CAN GPIO I/O General purpose PS1 TXD I/O Serial Communication Interface transmit pin PWM7 I/O PWM channel 7, mappable through software GPIO I/O General purpose PS0 RXD I/O Serial Communication Interface receive pin PWM6 O PWM channel 6, mappable through software GPIO I/O General purpose T PT[7:4] FP[16:13] O LCD segment driver output GPIO KWT[7:4] I Key Wakeup IOC0[7:4] I/O Timer0 Channels 7-4 GPIO I/O General purpose PT[3:0] FP[11:8] O LCD segment driver output KWT[3:0] I Key Wakeup IOC1[7:4] I/O Timer1 Channels 7-4 GPIO I/O General purpose Port Pin Name Pin Function & Priority1 I/O Description Pin Function after Reset |
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