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SC9S12HY64J0CLL 数据表(PDF) 56 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLL 数据表(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 56 Freescale Semiconductor H PH[7:4] FP[26:23] O LCD frontplane segment driver output GPIO GPIO I/O General purpose PH[3] FP[22] O LCD frontplane segment driver output SDA I/O SDA of IIC, mappable through software SS I/O SS of SPI, mappable through software GPIO I/O General purpose PH[2] FP[21] O LCD frontplane segment driver output SCK I/O SCK of SPI, mappable through software ECLK O Free-running clock at bus clock rate or programmable down-scaled bus clock GPIO I/O General purpose PH[1] FP[20] O LCD frontplane segment driver output MOSI I/O MOSI of SPI, mappable through software GPIO I/O General purpose PH[0] FP[19] O LCD frontplane segment driver output SCL I/O SCL of IIC, mappable through software MISO I/O MISO of SPI, mappable through software GPIO I/O General purpose P PP[7:0] FP[7:0] O LCD frontplane segment driver output GPIO PWM[7:0] I/O Pulse Width Modulator channel 7 - 0 GPIO I/O General purpose R PR[7] FP[27] I LCD frontplane segment driver output GPIO GPIO I/O General purpose PR[6] FP[18] I LCD frontplane segment driver output SCL I/O SCL of IIC, mappable through software GPIO I/O General purpose PR[5] FP[17] I LCD frontplane segment driver output SDA I/O SDA of IIC, mappable through software GPIO I/O General purpose PR[4] FP[12] I LCD frontplane segment driver output GPIO I/O General purpose PR[3:2] KWR[3:2] I Key Wakeup IOC1[7:6] I/O TIM1 channel, mappable through software GPIO I/O General purpose PR[1:0] KWR[1:0] I Key Wakeup IOC0[7:6] I/O TIM0 channel, mappable through software GPIO I/O General purpose Port Pin Name Pin Function & Priority1 I/O Description Pin Function after Reset |
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