xRESETn and xENBLn Operation

DRV8821

AOUTx

BOUTx

FULL STEP

STEP

1/4 STEP

1/8 STEP

STEP ANGLE

CURRENT

CURRENT

xUSM = 00

xUSM = 01

xUSM = 10

xUSM = 11

(DEGREES)

(% FULL-SCALE) (% FULL-SCALE)

1

1

1

100

0

0

2

98

20

11.25

2

3

92

38

22.5

4

83

56

33.75

1

2

3

5

71

71

45 (home state)

6

56

83

56.25

4

7

38

92

67.5

8

20

98

78.75

3

5

9

0

100

90

10

–20

98

101.25

6

11

–38

92

112.5

12

–56

83

123.75

2

4

7

13

–71

71

135

14

–83

56

146.25

8

15

–92

38

157.5

16

–98

20

168.75

5

9

17

–100

0

180

18

–98

–20

191.25

10

19

–92

–38

202.5

20

–83

–56

213.75

3

6

11

21

–71

–71

225

22

–56

–83

236.25

12

23

–38

–92

247.5

24

–20

–98

258.75

7

13

25

0

–100

270

26

20

–98

281.25

14

27

38

–92

292.5

28

56

–83

303.75

4

8

15

29

71

–71

315

30

83

–56

326.25

16

31

92

–38

337.5

32

98

–20

348.75

The xRESETn pin, when driven active low, resets the step table to the home position. It also disables the

H-bridge drivers. The xSTEP input is ignored while xRESETn is active. Note that there is a separate xRESETn

pin for each motor; each acts only on one of the two motor controllers.

The xENABLEn pin is used to control the output drivers. When xENBLn is low, the output H-bridges are enabled.

When xENBLn is high, the H-bridges are disabled and the outputs are in a high-impedance state.. Note that

there is a separate xENBLn pin for each motor; each acts only on one of the two motor drivers.

Note that when xENBLn is high, the input pins and control logic, including the indexer (xSTEP and xDIR pins) are

still functional.

Driving both ABENBLn and CDENBLn high will put the device into a low power sleep state. In this state, the

H-bridges are disabled, the gate drive charge pump is stopped, and all internal clocks are stopped. In this state

all inputs are ignored until one or both of the xENBLn pits return active low.

10

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