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CPC7582MATR 数据表(PDF) 15 Page - Clare, Inc. |
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CPC7582MATR 数据表(HTML) 15 Page - Clare, Inc. |
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15 / 19 page ![]() CPC7582 R05 www.clare.com 15 switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See application note AN-144, Impulse Noise Benefits of Line Card Access Switches. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ringing generator is recommended. 2.6 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7582. CPC7582 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7582BC exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. 2.7 Battery Voltage Monitor The CPC7582 also uses the VBAT voltage to monitor battery voltage. If battery voltage is lost, the CPC7582 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, and remains in the all-off state until the battery voltage goes more negative than –15 V. This battery monitor feature draws a small current from the battery (less than 1 μA typical) and will add slightly to the device’s overall power dissipation. 2.8 Protection 2.8.1 Diode Bridge/SCR The CPC7582 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the voltage at VBAT, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see “Protection Circuitry Electrical Specifications” on page 10) of the SCR must be less negative than the VBAT voltage. If the VBAT voltage is less negative than the SCR on voltage or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the VBAT voltage by two to four volts, steering the current to ground. 2.8.2 Current Limiting function If a lightning strike transient occurs when the device is in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of the active switches during the talk state. During the talk state, when a 1000V 10x1000 μs pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 μs. If a power-cross fault occurs with the device in the talk state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault, the limited current measured at pin 3 (TLINE) and pin 14 (RLINE) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 2.9 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +VDD. |
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