CPC7592MATR datasheet(14/20 Pages) CLARE

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CPC7592

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2.3.5 Break-Before-Make Operation - All Versions

The second break-before-make method for the

CPC7592xA/B is also the only method available for

the CPC7592xC. As shown in “CPC7592xA and

CPC7592xB Truth Table” on page 10 and

“CPC7592xC Truth Table” on page 10, the

bi-directional TSD interface disables all of the

CPC7592 switches when pulled to a logic low.

Although logically disabled, an active (closed) ringing

switch (SW4) will remain closed until the next zero

crossing current event.

As shown in the table “Break-Before-Make Ringing to

Talk Transition Logic Sequence for all Versions” on

page 14, this operation is similar to the one shown in

“Break-Before-Make Operation - All Versions” on

page 14, except in the method used to select the all off

state, and in when the INRINGING and INTEST inputs

are reconfigured for the talk state.

Pull TSD to a logic low to end the ringing state.

This opens the ringing return switch (SW3) and

prevents any other switches from closing.

Keep TSD low for at least one-half the duration of

the ringing cycle period to allow sufficient time for

a zero crossing current event to occur and for the

circuit to enter the break-before-make state.

During the TSD low period, set the INRINGING and

INTEST inputs to the talk state (0, 0).

Release TSD, allowing the internal pull-up to

activate the break switches.

When using TSD as an input, the two recommended

states are “0” which overrides the logic input pins and

forces an all off state and “Z” which allows normal

switch control via the logic input pins. This requires the

use of an open-collector or open-drain type buffer.

Forcing TSD to a logic high disables the thermal

shutdown circuit and is therefore not recommended as

this could lead to device damage or destruction in the

presence of excessive tip or ring potentials.

Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions

2.4 Data Latch

The CPC7592 has an integrated transparent data

latch. The latch enable operation is controlled by TTL

logic input levels at the LATCH pin. Data input to the

latch is via the input pins INRINGING and INTEST while

the output of the data latch are internal nodes used for

state control. When the LATCH enable control pin is at

a logic 0 the data latch is transparent and the input

control signals flow directly through the data latch to

the state control circuitry. A change in input will be

reflected by a change in the switch state.

Whenever the LATCH enable control pin is at logic 1,

the data latch is active and data is locked. Subsequent

changes to the input controls INRINGING and INTEST

will not result in a change to the control logic or affect

the existing switch state.

The switches will remain in the state they were in

when the LATCH changes from logic 0 to logic 1 and

will not respond to changes in input as long as the

LATCH is at logic 1. However, neither the TSD input

nor the TSD output control functions are affected by

the latch function. Since internal thermal shutdown

State

INRINGING

INTEST

LATCH

TSD

Timing

Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing

Off

All-Off

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero current to

turn off.

Off

Break-

Before-

Make

SW4 has opened

Off

Talk

Close Break Switches

Off

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