CPC7593MATR datasheet(20/24 Pages) CLARE

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CPC7593

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R04

For power induction or power-cross fault conditions,

the positive cycle of the transient is clamped to a diode

drop above ground and the fault current is directed to

ground. The negative cycle of the transient will cause

the SCR to conduct when the voltage exceeds the

VBAT reference voltage by two to four volts, steering

the fault current to ground.

Note: Neither the CPC7593xB or the CPC7593xD

contains the protection SCR but instead uses a diode

bridge to clamp both polarities of a fault transient.

These diodes direct the negative potential’s fault

current to the VBAT pin.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the talk state, the current is passed along the line to

the integrated protection circuitry and restricted by the

dynamic current limit response of the active switches.

During the talk state when a 1000V 10x1000

μS pulse

(GR-1089-CORE lightning) is applied to the line

though a properly clamped external protector, the

current seen at TLINE or RLINE will be a pulse with a

typical magnitude of 2.5 A and a duration of less than

0.5

μs.

If a power-cross fault occurs with the device in the talk

state, the current is passed though the break switches

SW1 and SW2 on to the integrated protection circuit

but is limited by the dynamic DC current limit response

of the two break switches. The DC current limit

specified over temperature is between 80mA and

425mA, and the circuitry has a negative temperature

coefficient. As a result, if the device is subjected to

extended heating due to a power cross fault condition,

the measured current into TLINE or RLINE will decrease

as the device temperature increases. If the device

temperature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

enter the all-off state.

2.10 Thermal Shutdown

The thermal shutdown mechanism will activate when

the device die temperature reaches a minimum of

110° C, placing the device in the all-off state

regardless of INRINGING, INTESTin and INTESTout logic

inputs. During thermal shutdown events the TSD pin

will output a logic low with a nominal 0 V level. A logic

high is output from the TSD pin during normal

operation with a typical output level equal to VDD.

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will

typically not activate. But in an extended power-cross

event, the device temperature will rise and the thermal

shutdown mechanism will activate forcing the switches

to the all-off state. At this point the current measured

into TLINE or RLINE will drop to zero. Once the device

enters thermal shutdown it will remain in the all-off

state until the temperature of the die drops below the

deactivation level of the thermal shutdown circuit. This

permits the device to return to normal operation. If the

transient has not passed, current will again flow up to

the value allowed by the dynamic DC current limiting

of the switches and heating will resume, reactivating

the thermal shutdown mechanism. This cycle of

entering and exiting the thermal shutdown mode will

continue as long as the fault condition persists. If the

magnitude of the fault condition is great enough, the

external secondary protector will activate shunting the

fault current to ground.

The thermal shutdown mechanism of the CPC7593

cannot be disabled by forcing a logic 1 to TSD.

Therefore, only an open-collector or open-drain type

interface should be used to control the TSD pin’s input

function.

2.11 External Protection Elements

The CPC7593 requires only over voltage secondary

protection on the loop side of the device. The

integrated protection feature described above negates

the need for additional external protection on the SLIC

side. The secondary protector must limit voltage

transients to levels that do not exceed the breakdown

voltage or input-output isolation barrier of the

CPC7593. A foldback or crowbar type protector is

recommended to minimize stresses on the CPC7593.

Consult Clare’s application note, AN-100, “Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interfaces” for equations related

to the specifications of external secondary protectors,

fused resistors and PTCs.

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