TLE8201R datasheet(5/45 Pages) INFINEON

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TLE 8201R

Pin Configuration

Data Sheet Rev. 2.0

2006-06-07

2.2

Pin Definitions and Functions

Symbol

Function

cooling

tab

GND

Cooling tab, internally connected to GND; to reduce thermal

resistance place cooling areas and thermal vias on PCB.

1, 18,

19, 36

GND

Ground; internally connected to cooling tab (heat slug).

2OUT5

Power-Output of half-bridge 5; DMOS half-bridge

3OUT6

Power-Output of half-bridge 6; DMOS half-bridge.

4, 15, 23,

26, 30, 33

Power supply; needs decoupling capacitors to GND. > 47µF

electrolytic in parallel with 100nF ceramic is recommended. All

Vs pins must be connected externally

5INH

Inhibit; active low. Sets the device in sleep mode with low

current consumption when left open or pulled to LOW. Has an

internal pull down current source

6PWM1

Logic Input for direct power stage control; direct input to

control the high-side switches selected by the SPI xsel1 bits in

control register CtrlReg01

7PWM2

Logic Input for direct power stage control; direct input to

control the switches selected by the SPI xsel2 bits in control

8ISO

Current sense output; Mirrors the current of the high-side

switch selected by the current sense multiplexer control bits ISx

9Vcc

Logic Supply Voltage; needs decoupling capacitors to GND

(pin 1). 10µF electrolytic in parallel with 10nF ceramic is

recommended

Serial Data Output; Transfers data to the master when the chip

is selected by CSN=LOW. Data transmission is synchronized by

CLK, DO state is changed on the rising edge of CLK. The most

significant bit (MSB) is transferred first. The pin is tristated as

long as CSN=HIGH

CLK

Serial Data Clock Input; Receives the clock signal from the

master and clocks the SPI shift register. Has an internal pull

down current source

CSN

Serial Port Chip Select Not Input; SPI communication is

enabled by pulling CSN to LOW. CLK must be LOW during the

transition of CSN. The CSN-pin has an internal pull-up current

source

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