ATtiny5 datasheet(8/20 Pages) ATMEL

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8127CS–AVR–10/09

ATtiny4/5/9/10

5. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add without Carry

← Rd + Rr

Z,C,N,V,S,H

ADC

Rd, Rr

Add with Carry

← Rd + Rr + C

Z,C,N,V,S,H

SUB

Rd, Rr

Subtract without Carry

← Rd - Rr

Z,C,N,V,S,H

SUBI

Rd, K

Subtract Immediate

← Rd - K

Z,C,N,V,S,H

SBC

Rd, Rr

Subtract with Carry

← Rd - Rr - C

Z,C,N,V,S,H

SBCI

Rd, K

Subtract Immediate with Carry

← Rd - K - C

Z,C,N,V,S,H

AND

Rd, Rr

Logical AND

← Rd • Rr

Z,N,V,S

ANDI

Rd, K

Logical AND with Immediate

← Rd • K

Z,N,V,S

Rd, Rr

Logical OR

← Rd v Rr

Z,N,V,S

ORI

Rd, K

Logical OR with Immediate

← Rd v K

Z,N,V,S

EOR

Rd, Rr

Exclusive OR

← Rd ⊕ Rr

Z,N,V,S

COM

One’s Complement

← $FF − Rd

Z,C,N,V,S

NEG

Two’s Complement

← $00 − Rd

Z,C,N,V,S,H

SBR

Rd,K

Set Bit(s) in Register

← Rd v K

Z,N,V,S

CBR

Rd,K

Clear Bit(s) in Register

← Rd • ($FFh - K)

Z,N,V,S

INC

Increment

← Rd + 1

Z,N,V,S

DEC

Decrement

← Rd − 1

Z,N,V,S

TST

Test for Zero or Minus

← Rd • Rd

Z,N,V,S

CLR

Clear Register

← Rd ⊕ Rd

Z,N,V,S

SER

Set Register

← $FF

None

BRANCH INSTRUCTIONS

RJMP

Relative Jump

← PC + k + 1

None

IJMP

Indirect Jump to (Z)

PC(15:0)

← Z, PC(21:16) ← 0None

RCALL

Relative Subroutine Call

← PC + k + 1

None

3/4

ICALL

Indirect Call to (Z)

PC(15:0)

← Z, PC(21:16) ← 0None

3/4

RET

Subroutine Return

← STACK

None

4/5

RETI

Interrupt Return

← STACK

4/5

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC

← PC + 2 or 3

None

1/2/3

Rd,Rr

Compare

− Rr

Z, C,N,V,S,H

CPC

Rd,Rr

Compare with Carry

− Rr − C

Z, C,N,V,S,H

CPI

Rd,K

Compare with Immediate

− K

Z, C,N,V,S,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC

← PC + 2 or 3

None

1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC

← PC + 2 or 3

None

1/2/3

SBIC

A, b

Skip if Bit in I/O Register Cleared

if (I/O(A,b)=0) PC

← PC + 2 or 3

None

1/2/3

SBIS

A, b

Skip if Bit in I/O Register is Set

if (I/O(A,b)=1) PC

← PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC

←PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC

←PC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC

← PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC

← PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC

← PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC

← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC

← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC

← PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC

← PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC

← PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N

⊕ V= 0) then PC ← PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N

⊕ V= 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC

← PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC

← PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC

← PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC

← PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC

← PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC

← PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC

← PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC

← PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS

LSL

Logical Shift Left

Rd(n+1)

← Rd(n), Rd(0) ← 0

Z,C,N,V,H

LSR

Logical Shift Right

Rd(n)

← Rd(n+1), Rd(7) ← 0

Z,C,N,V

ROL

Rotate Left Through Carry

Rd(0)

←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V,H

ROR

Rotate Right Through Carry

Rd(7)

←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

ASR

Arithmetic Shift Right

Rd(n)

← Rd(n+1), n=0..6

Z,C,N,V

SWAP

Swap Nibbles

Rd(3..0)

←Rd(7..4),Rd(7..4)←Rd(3..0)

None

BSET

Flag Set

SREG(s)

← 1

SREG(s)

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