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ATtiny5 数据表(PDF) 9 Page - ATMEL Corporation

部件名 ATtiny5
功能描述  8-bit Microcontroller with 512/1024 Bytes In-System Programmable Flash
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

ATtiny5 数据表(HTML) 9 Page - ATMEL Corporation

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9
8127CS–AVR–10/09
ATtiny4/5/9/10
BCLR
s
Flag Clear
SREG(s)
← 0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
← 1None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)
← 0None
1
BST
Rr, b
Bit Store from Register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
← TNone
1
SEC
Set Carry
C
← 1C
1
CLC
Clear Carry
C
← 0
C
1
SEN
Set Negative Flag
N
← 1N
1
CLN
Clear Negative Flag
N
← 0
N
1
SEZ
Set Zero Flag
Z
← 1Z
1
CLZ
Clear Zero Flag
Z
← 0
Z
1
SEI
Global Interrupt Enable
I
← 1I
1
CLI
Global Interrupt Disable
I
← 0
I
1
SES
Set Signed Test Flag
S
← 1S
1
CLS
Clear Signed Test Flag
S
← 0
S
1
SEV
Set Two’s Complement Overflow.
V
← 1V
1
CLV
Clear Two’s Complement Overflow
V
← 0
V
1
SET
Set T in SREG
T
← 1T
1
CLT
Clear T in SREG
T
← 0
T
1
SEH
Set Half Carry Flag in SREG
H
← 1H
1
CLH
Clear Half Carry Flag in SREG
H
← 0
H
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Copy Register
Rd
← Rr
None
1
LDI
Rd, K
Load Immediate
Rd
← KNone
1
LD
Rd, X
Load Indirect
Rd
← (X)
None
1/2
LD
Rd, X+
Load Indirect and Post-Increment
Rd
← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Decrement
X
← X - 1, Rd ← (X)
None
2/3
LD
Rd, Y
Load Indirect
Rd
← (Y)
None
1/2
LD
Rd, Y+
Load Indirect and Post-Increment
Rd
← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Decrement
Y
← Y - 1, Rd ← (Y)
None
2/3
LD
Rd, Z
Load Indirect
Rd
← (Z)
None
1/2
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
← Z - 1, Rd ← (Z)
None
2/3
LDS
Rd, k
Store Direct from SRAM
Rd
← (k)
None
1
ST
X, Rr
Store Indirect
(X)
← Rr
None
1
ST
X+, Rr
Store Indirect and Post-Increment
(X)
← Rr, X ← X + 1
None
1
ST
- X, Rr
Store Indirect and Pre-Decrement
X
← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y)
← Rr
None
1
ST
Y+, Rr
Store Indirect and Post-Increment
(Y)
← Rr, Y ← Y + 1
None
1
ST
- Y, Rr
Store Indirect and Pre-Decrement
Y
← Y - 1, (Y) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z)
← Rr
None
1
ST
Z+, Rr
Store Indirect and Post-Increment.
(Z)
← Rr, Z ← Z + 1
None
1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z
← Z - 1, (Z) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k)
← Rr
None
1
IN
Rd, A
In from I/O Location
Rd
← I/O (A)
None
1
OUT
A, Rr
Out to I/O Location
I/O (A)
← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK
← Rr
None
2
POP
Rd
Pop Register from Stack
Rd
← STACK
None
2
MCU CONTROL INSTRUCTIONS
BREAK
Break
(see specific descr. for Break)
None
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR)
None
1
Mnemonics
Operands
Description
Operation
Flags
#Clocks



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