AT25DF321 datasheet(29/37 Pages) ATMEL

29 / 37 page

3669B–DFLASH–6/09

AT25DF321

Notes: 1. Not 100% tested (value guaranteed by design and characterization).

2. 15 pF load at 70 MHz, 30 pF load at 66 MHz.

3. Only applicable as a constraint for the Write Status Register command when SPRL = 1.

12.4 AC Characteristics

Symbol

Parameter

Min

Max

Units

fSCK

Serial Clock (SCK) Frequency

MHz

fRDLF

SCK Frequency for Read Array (Low Frequency – 03h opcode)

MHz

tSCKH

SCK High Time

6.8

tSCKL

SCK Low Time

6.8

tSCKR

(1)

SCK Rise Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

tSCKF(1)

SCK Fall Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

tCSH

Chip Select High Time

tCSLS

Chip Select Low Setup Time (relative to SCK)

tCSLH

Chip Select Low Hold Time (relative to SCK)

tCSHS

Chip Select High Setup Time (relative to SCK)

tCSHH

Chip Select High Hold Time (relative to SCK)

tDS

Data In Setup Time

tDH

Data In Hold Time

tDIS

(1)

Output Disable Time

6ns

tV(2)

Output Valid Time

6ns

tOH

Output Hold Time

tHLS

HOLD Low Setup Time (relative to SCK)

tHLH

HOLD Low Hold Time (relative to SCK)

tHH

HOLD High Setup Time (relative to SCK)

tHHH

HOLD High Hold Time (relative to SCK)

tHLQZ(1)

HOLD Low to Output High-Z

tHHQX

(1)

HOLD High to Output Low-Z

tWPS

(1)(3)

Write Protect Setup Time

tWPH(1)(3)

Write Protect Hold Time

100

tSECP

(1)

Sector Protect Time (from Chip Select High)

tSECUP

(1)

Sector Unprotect Time (from Chip Select High)

tEDPD(1)

Chip Select High to Deep Power-Down

µs

tRDPD

(1)

Chip Select High to Standby Mode

µs

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