MAXQ3180-RAN+ datasheet(21/101 Pages) MAXIM

21 / 101 page

Low-Power, Multifunction, Polyphase AFE

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SPI clock idle state is low, and data is shifted in and out

on the rising edge of SCLK. Once SPI communication

with the MAXQ3180 has been established, it is possible

to alter the CKPOL and CKPHA format settings (as well

as changing the SSEL signal from active low to active

high) if desired by writing to the R_SPICF mirror register

and then reading from the special command register

UPD_SFR to copy the R_SPICF value into the internal

SPI configuration register.

Whenever the active clock edge is used for sampling

(CKPHA = 0), the transfer cycle must be started with

assertion of the SSEL signal. This requirement means

that the SSEL signal be deasserted and reasserted

between successive transfers. Conversely, when the

inactive edge is used for sampling (CKPHA = 1), the

SSEL signal may remain low through successive

transfers, allowing the active clock edge to signal the

start of a new transfer.

The clock rate used for the SPI interface is determined

by the bus master, since the MAXQ3180 always oper-

ates as an SPI slave device. However, the maximum

clock rate is limited by the system clock frequency of

the MAXQ3180. For proper communications operation,

the SPI clock frequency used by the master must be

less than or equal to the MAXQ3180’s clock frequency

divided by 4. For example, when the MAXQ3180 is run-

ning at 8MHz, the SPI clock frequency must be 2MHz

or less. And if the MAXQ3180 is running in LOWPM

Mode (or if the crystal is still warming up), the SPI clock

frequency must remain at 250kHz or less for proper

communications operation.

In addition to limiting the overall SPI bus clock rate, the

master must also include a communications delay fol-

lowing each byte transmit/receive cycle. This delay,

which provides the MAXQ3180 with time to process an

ADC sample, should be a minimum of 400 system

clocks. With default settings and running at 8MHz, this

delay time is 50μs. Reducing the system clock frequen-

cy to 1MHz (LOWPM mode) would increase this delay

period by a factor of 8 to 400μs.

SPI Communications Protocol

All transactions between the master and the

MAXQ3180 consist of the master writing to or reading

from one of the MAXQ3180’s registers. To the host, the

MAXQ3180 looks like a memory array that consists of

both RAM and ROM. This is because the ROM firmware

in the MAXQ3180 reads its operational parameters from

RAM and places its results in RAM. Consequently, con-

figuring a MAXQ3180 is as simple as performing a

block write to its RAM locations.

Some read-only memory locations in the MAXQ3180

trigger actions within the device to calculate electricity-

metering results on the fly. The specific function and

purpose of RAM and virtual ROM locations are given in

the register map. There are several different categories

of internal registers on the MAXQ3180.

• RAM Registers. The values of these registers are

stored in the internal RAM of the MAXQ3180. Some

can be read and written by the master, while others

are read-only. RAM registers are either 2 or 4 bytes

long (16 or 32 bits), although in some registers not all

the bits have defined values. Read/write registers are

generally either status/flag registers (which can be

written by either the MAXQ3180 or the master), con-

figuration registers (which are written by the master

and read by the MAXQ3180 firmware), or data regis-

ters (which are read-only and are written by the

MAXQ3180 firmware and read by the master).

• Virtual Registers. These read-only registers are not

stored in RAM; instead, they contain values that are

calculated on the fly by the MAXQ3180 firmware

when the master reads them. These registers are

used by the master to obtain values such as phase

A, B, and C active, reactive, and apparent power;

power factor; and RMS voltage and current, which

are calculated from currently collected data on an

as-needed basis. Most virtual registers are 8 bytes in

length.

• Hardware Registers. These registers control core

functions of the MAXQ3180 including the ADC and

the SPI slave bus controller. Each of these registers

(R_ACFG, R_ADCRATE, R_ADCACQ, R_SPICF, and

OPMODE0 (bit 4, EXTCLK only)) has a register loca-

tion in RAM that “shadows” the value of the hardware

ter must first read from the special command register

UPD_MIR (A00h) to copy the values from the hard-

ware registers to the mirror registers in RAM, and

then the mirror register in RAM can be read. To write

to a hardware register, the master reverses the

process by writing to the mirror RAM register and

then reading from the special command register

UPD_SFR (900h) to copy the values from the mirror

registers to the hardware registers.

• Special Command Registers. These registers

(UPD_SFR and UPD_MIR) do not return meaningful

data when read but instead trigger an operation.

Reading UPD_SFR causes values to be copied from

the mirror registers to hardware, and reading

UPD_MIR causes values to be copied from the hard-

ware to mirror registers.

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