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MAXQ3181-RAN+ 数据表(PDF) 33 Page - Maxim Integrated Products

部件名 MAXQ3181-RAN+
功能描述  Low-Power, Active Energy, Polyphase AFE
PDF  84 Pages
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制造商  MAXIM [Maxim Integrated Products]
网页  https://www.maximintegrated.com/en.html
标志 MAXIM - Maxim Integrated Products

MAXQ3181-RAN+ 数据表(HTML) 33 Page - Maxim Integrated Products

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Low-Power, Active Energy, Polyphase AFE
______________________________________________________________________________________
33
CFP Pulse Width (PLS1_WD) (0x020)
This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the
active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides
a pulse width of about 50ms.
Bit:
15
14
13
12
11
10
9
8
Name:
CFP Pulse-Width High Byte
Reset:
0x00
Bit:
7
6
5
4
3
2
1
0
Name:
CFP Pulse-Width Low Byte
Reset:
0x9C
Meter Pulse Configuration
Pulse Configuration—CFP Output (PLSCFG1) (0x01E)
This register selects which phases are included in the CFP pulse output and also selects which quantity is accumu-
lated to drive the pulse output.
Bit:
7
6
5
4
3
2
1
0
Name:
QNSEL
PHASEC
PHASEB
PHASEA
Reset:
0x0
0
0
0
BIT
NAME
FUNCTION
7:3
QNSEL
CFP Pulse Output Source Select. This five-bit field determines what meter value will be accumulated in
each of the phases to produce the CFP pulse output. All other values are reserved.
00000 = Net real energy
00001 = Absolute real energy
00100 = Apparent energy
00110 = IRMS
00111 = VRMS
01000 = Real energy delivered to load
01001 = Real energy delivered to line
2
PHASEC
CFP Phase C Inclusion. When this bit is set, phase C is included in CFP pulse generation.
1
PHASEB
CFP Phase B Inclusion. When this bit is set, phase B is included in CFP pulse generation.
0
PHASEA
CFP Phase A Inclusion. When this bit is set, phase A is included in CFP pulse generation.



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