Functional Description

The LM5033 High Voltage PWM controller contains all of the

features needed to implement Push-Pull and Bridge topolo-

gies, using voltage-mode control in a small 10 pin package.

Features included are: startup regulator, precision 2.5V ref-

erence output, current limit detection, alternating gate driv-

ers, sync capability, thermal shutdown, softstart, and remote

shutdown. This high speed IC has total propagation delays

DC-DC converter, or a voltage controlled closed loop con-

verter. The Functional Block Diagram is shown in Figure 1.

High Voltage Start-Up Regulator

(Pins 1, 4)

The LM5033 contains an internal high voltage startup regu-

lator. The input pin (V

voltages as high as 90V for normal operation, and can

withstand transients to 100V. The regulator output at V

CC

(9.6V) is internally current limited and sources a minimum of

20mA. Upon power up, the capacitor at V

providing a time delay while internal circuits stabilize. When

V

sor (typically 9.5V), the under-voltage sensor resets, en-

abling the output drivers, although the PWM duty cycle will

initially be at zero. As the Softstart capacitor then charges up

(described below) the output duty cycle will increase until

regulated by the PWM control loop. The value of the V

CC

capacitor which affects the above mentioned delay depends

on the total system design and its start-up characteristics.

The recommended range of values for the V

0.1 to 50µF.

The lower threshold of the under-voltage sensor is typically

at 6.8V. If V

and the softstart capacitor is discharged. When V

increased above the upper threshold the outputs are en-

abled, and the softstart sequence repeats.

The LM5033’s internal power dissipation can be reduced by

powering V

by means of an auxiliary transformer winding which is diode

connected to the V

controller completes the start-up sequence. The externally

applied V

off. The under-voltage sensor circuit will still function in this

mode, requiring that the external V

that V

V

mance Characteristics (I

If a fault condition occurs such that the external supply to

V

limited as to not exceed the regulator’s current limit, or the

maximum power dissipation of the IC. An external start-up or

other bias rail can be used instead of the internal start-up

regulator by connecting the V

and feeding the external bias voltage (10-15V) into that

node.

A thermal shutdown protection will activate if the die tem-

OUT2), and shutting down the V

temperature has reduced below 150˚C (typical hysteresis =

15˚C) the V

will initiate.

Reference (Pin 2)

The pin is internally connected to an NMOS FET drain at the

buffer amplifier’s output, allowing it to sink, but not source

current. An external pullup resistor is required. Current into

the pin must be limited to less than 20 mA to maintain

regulation. See the graph in the Typical Performance Char-

acteristics.

During start-up if the pullup voltage is present before the

reference amplifier establishes regulation, the voltage on pin

2 must not exceed 5.5V. If this reference is not used the Ref

pin can float or be connected to ground.

PWM Comparator (Pin 3), Duty

Cycle and Deadtime

The PWM comparator compares an internal ramp signal (0 -

0.65V) with the loop error voltage derived from the Comp pin

(pin 3). The Comp voltage is typically set by an external error

amplifier through an optocoupler for closed loop applica-

tions. Internally, the voltage at the Comp pin passes through

two level shifting diodes, and a gain reducing 3:1 resistor

divider. The output of the PWM comparator provides the

pulse width information to the output drivers (Out1 and

Out2). This comparator is optimized for speed in order to

achieve minimum discernable duty cycles. The output duty

cycle is 0% for V

3.5V. See the Typical Performance Characteristics. The

maximum duty cycle for each output is limited to less than

50% due to the forced deadtime. The typical deadtime be-

tween the falling edge of one gate driver output and the

rising edge of the other gate driver output is 135 ns, and

does not vary with frequency. The maximum duty cycle for

each output can be calculated from:

where T

time. For example, if the oscillator frequency is 200 kHz,

each output will cycle at 100 kHz, and T

nominal deadtime of 135 ns, the maximum duty cycle at this

frequency is 48.65%. Using the minimum deadtime of 85 ns,

the maximum duty cycle increases to 49.15%.

When the Softstart pin (pin 10) is pulled down (internally or

externally) the Comp pin voltage is pulled down with it, with

a difference of 0.5V. When the Softstart pin voltage in-

creases the Comp voltage is allowed to increase, pulled up

by an internal 5.2V supply through a 5k

Ω resistor.

In an open loop application, such as an intermediate bus

converter, pin 3 can be left open resulting in maximum duty

cycle at the output drivers .

Current Sense (Pin 8)

The current sense circuit is intended to protect the power

converter when an abnormal primary current is sensed by

initiating a low duty cycle hiccup mode. When the threshold

(0.5V) at Pin 8 is exceeded the outputs are disabled, and the

softstart capacitor (at pin 10) is internally discharged. When

the softstart capacitor is fully discharged and the voltage at

the CS pin is below 0.5V, the outputs are re-enabled allowing

the softstart capacitor voltage and the output duty cycle to

increase.

www.national.com

8