Data brief

For further information contact your local STMicroelectronics sales office.

December 2009

Doc ID 16899 Rev 1

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STiDP880

iDP to LVDS converter

Features

– Compliant with proposed iDP specification

– 3.24 Gbps per lane

– 1, 2, or 4 lanes

– HPD pulse assertion as per proposed iDP

standard

(FHD) 120 Hz/10-bit color

panels

– Quad LVDS interface up to 100 MHz per

channel (400 MHz pixel rate)

– High speed dual-link LVDS up to 150 MHz

per channel (300 MHz pixel rate)

– Supports JEIDA, non-JEIDA, VESA pixel

data mappings

Reset (ASSR) for premium contents reception

reduction

UTP type cables

– 164 LFBGA (12 x 12 mm/0.8 mm pitch)

– HF and RoHS compliant

– 3.3 V I/O; 1.2 V core

– 2 KV HBM, 200 V MM, 600V CDM

Applications

Q-LVDS

output

4 Main Lanes

I2C Host

Interface

Bus Formatter

LVDS Outputs

Internal

DisplayPort

Receiver

HPD

iDP Input

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