AD5541A/AD5542A/AD5512A

Preliminary Technical Data

Rev. P

rA | Page 16 of 24

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5541/AD5542 is via a

serial bus that uses standard protocol that is compatible with

DSP processors and microcontrollers. The communications

channel requires a 3- or 4-wire interface consisting of a clock

signal, a data signal and a synchronization signal. The

AD5541/AD5542 require a 16-bit data-word with data valid on

the rising edge of SCLK. The DAC update can be done

automatically when all the data is clocked in or it can be done

under control of the LDAC (AD5542 only).

AD5541/AD5542 TO ADSP-2101/ADSP-2103

INTERFACE

Figure 33 shows a serial interface between the AD5541/AD5542

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

should be set to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 are programmed through

the SPORT control register and should be configured as follows:

internal clock operation, active low framing, 16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out

on each rising edge of the serial clock, an inverter is required

between the DSP and the DAC, because the AD5541/AD5542

clock data in on the falling edge of the SCLK.

LDAC**

CS

DIN

SCLK

FO

TFS

DT

SCLK

AD5541/

AD5542*

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 33. AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface

AD5541/AD5542 TO 68HC11/68L11 INTERFACE

Figure 34 shows a serial interface between the AD5541/AD5542

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the SCLK of the DAC, and the MOSI output drives

the serial data line serial DIN. The CS signal is driven from one

of the port lines. The 68HC11/68L11 is configured for master

mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing

on the MOSI output is valid on the rising edge of SCK.

LDAC**

CS

DIN

SCLK

PC6

PC7

MOSI

SCK

AD5541/

AD5542*

68HC11/

68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 34. AD5541/AD5542 to 68HC11/68L11 Interface

AD5541/AD5542 TO MICROWIRE INTERFACE

Figure 35 shows an interface between the AD5541/AD5542

and any MICROWIRE-compatible device. Serial data is shifted

out on the falling edge of the serial clock and into the AD5541/

AD5542 on the rising edge of the serial clock. No glue logic is

required because the DAC clocks data into the input shift

register on the rising edge.

DIN

SCLK

SO

SCLK

AD5541/

AD5542*

MICROWIRE*

*ADDITIONAL PINS OMITTED FOR CLARITY.

CS

CS

Figure 35. AD5541/AD5542 to MICROWIRE Interface

AD5541/AD5542 TO 80C51/80L51 INTERFACE

A serial interface between the AD5541/AD5542 and the 80C51/

80L51 microcontroller is shown in Figure 36. TxD of the micro-

controller drives the SCLK of the AD5541/AD5542, and RxD

drives the serial data line of the DAC. P3.3 is a bit programmable

pin on the serial port that is used to drive CS.

The 80C51/80L51 provide the LSB first, whereas the AD5541/

AD5542 expects the MSB of the 16-bit word first. Care should

be taken to ensure the transmit routine takes this into account.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmit data in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. As the DAC requires a 16-bit

word, P3.3 must be left low after the first eight bits are transferred,

and brought high after the second byte is transferred. LDAC on

the AD5542 can also be controlled by the 80C51/ 80L51 serial

port output by using another bit programmable pin, P3.4.

LDAC**

CS

DIN

SCLK

P3.4

P3.3

RxD

TxD

AD5541/

AD5542*

80C51/

80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 36. AD5541/AD5542 to 80C51/80L51 Interface