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ADE7858 数据表(PDF) 67 Page - Analog Devices

部件名 ADE7858
功能描述  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7858 数据表(HTML) 67 Page - Analog Devices

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Preliminary Technical Data
ADE7858
Rev. PrA | Page 67 of 76
Bit
Location
Bit
Mnemonic
Default
value
Description
bit 0 (NLOAD) in STATUS1[31:0].
1
NLPHASE[1]
0
-0: phase B is out of no-load condition based on total active/reactive powers.
-1: phase B is in no load condition based on total active/reactive powers. Bit set together with
bit 0 (NLOAD) in STATUS1[31:0].
2
NLPHASE[2]
0
-0: phase C is out of no-load condition based on total active/reactive powers.
-1: phase C is in no load condition based on total active/reactive powers. Bit set together with
bit 0 (NLOAD) in STATUS1[31:0].
3-5
Reserved
000
Reserved. These bits are always 0.
6
VANLPHASE[0]
0
-0: phase A is out of no-load condition based on apparent power.
-1: phase A is in no load condition based on apparent power. Bit set together with bit 2
(VANLOAD) in STATUS1[31:0].
7
VANLPHASE[1]
0
-0: phase B is out of no-load condition based on apparent power.
-1: phase B is in no load condition based on apparent power. Bit set together with bit 2
(VANLOAD) in STATUS1[31:0].
8
VANLPHASE[2]
0
-0: phase C is out of no-load condition based on apparent power.
-1: phase C is in no load condition based on apparent power. Bit set together with bit 2
(VANLOAD) in STATUS1[31:0].
15-9
Reserved
000 0000
Reserved . These bits are always 0.
Table 34. COMPMODE register (address 0xE60E)
Bit
Location
Bit
Mnemonic
Default
value
Description
0
TERMSEL1[0]
1
Setting all TERMSEL1[2:0] to 1 signifies the sum of all 3 phases is included in CF1 output
Phase A is included in CF1 outputs calculations
1
TERMSEL1[1]
1
Phase B is included in CF1 outputs calculations
2
TERMSEL1[2]
1
Phase C is included in CF1 outputs calculations
3
TERMSEL2[0]
1
Setting all TERMSEL2[2:0] to 1 signifies the sum of all 3 phases is included in CF2 output
Phase A is included in CF2 outputs calculations
4
TERMSEL2[1]
1
Phase B is included in CF2 outputs calculations
5
TERMSEL2[2]
1
Phase C is included in CF2 outputs calculations
6
TERMSEL3[0]
1
Setting all TERMSEL3[2:0] to 1 signifies the sum of all 3 phases is included in CF3 output
Phase A is included in CF3 outputs calculations
7
TERMSEL3[1]
1
Phase B is included in CF3 outputs calculations
8
TERMSEL3[2]
1
Phase C is included in CF3 outputs calculations
10,9
ANGLESEL[1:0]
00
-00:the angles between phase voltages and phase currents are measured
-01: the angles between phase voltages are measured
-10: the angles between phase currents are measured
-11: no angles are measured
11
VNOMAEN
0
When this bit is 0, the apparent power on phase A is computed regularly. When this bit is 1, the
apparent power on phase A is computed using VNOM[23:0] register instead of regular measured
rms phase voltage.
12
VNOMBEN
0
When this bit is 0, the apparent power on phase B is computed regularly. When this bit is 1, the
apparent power on phase B is computed using VNOM[23:0] register instead of regular measured
rms phase voltage.
13
VNOMCEN
0
When this bit is 0, the apparent power on phase C is computed regularly. When this bit is 1, the
apparent power on phase C is computed using VNOM[23:0] register instead of regular measured
rms phase voltage.
14,15
Reserved
00
Reserved. These bits do not manage any functionality.
Table 35: GAIN register (address 0xE60F)
Bit
Mnemonic
Default
Description
2 to 0
PGA1[2:0]
000
Phase currents gain selection
-000: gain=1
-001: gain=2



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