ADE7858 datasheet(72/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 72 of 76

Bit Location

Bit Mnemonic

Default value

Description

-1: HSDC transmits the 32bit registers in 8bit packages, most significant bit first.

HGAP

-0: no gap is introduced between packages.

-1: a gap of 7 HCLK cycles is introduced between packages.

4,3

HXFER[1:0]

-00=HSDC transmits 16 32-bit words in the following order: IAWV, VAWV, IBWV, VBWV,

ICWV, VCWV, one 32-bit word equal to 0, AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR,

BVAR and CVAR

-01= HSDC transmits six instantaneous values of currents and voltages plus one 32-bit

word that is always equal to 0 in the following order: IAWV, VAWV, IBWV, VBWV, ICWV,

VCWV and one 32-bit word equal to 0.

-10= HSDC transmits 9 instantaneous values of phase powers: AVA, BVA, CVA, AWATT,

BWATT, CWATT, AVAR, BVAR and CVAR

-11=reserved. If set, the ADE7858 behaves as if HXFER[1:0]=00.

HSAPOL

-0: HSACTIVE output pin is active LOW.

-1: HSACTIVE output pin is active HIGH

7,6

Reserved

Reserved. These bits do not manage any functionality.

Table 44. CONFIG2 register (address 0xEC01)

Bit

Location

Bit

Mnemonic

Default

value

Description

EXTREFEN

When this bit is 0, signifies the internal voltage reference is used in the ADCs. When this bit is 1, an

external reference is connected to the pin 17 REF in/out

I2C_LOCK

When this bit is 0, the

SS /HSA pin can be toggled 3 times to activate the SPI port. If I2C is the active

serial port, this bit must be set to 1 to lock it in. From this moment on, spurious togglings of

the SS pin and an eventual switch into using SPI port is no longer possible. If SPI is the active serial

port, any write to CONFIG2[7:0] register locks the port. From this moment on, a switch into using I2C

port is no longer possible.

Once locked, the serial port choice is maintained when the ADE7858 changes PSMx, x=0,1,2,3

power modes.

7-2

Reserved

Reserved. These bits do not manage any functionality.

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