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ADP5022ACBZ-2-R7 数据表(PDF) 20 Page - Analog Devices |
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ADP5022ACBZ-2-R7 数据表(HTML) 20 Page - Analog Devices |
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20 / 28 page  ADP5022 Rev. A | Page 20 of 28 The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: () OUT SW IN RIPPLE C L f V V × × × × = 2 2π OUT SW RIPPLE C f I × × = 8 Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: RIPPLE RIPPLE COUT I V ESR ≤ The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 μF and a maximum of 40 μF. Table 8. Suggested 10 μF Capacitors Vendor Type Model Case Size Voltage Rating (V) Murata X5R GRM188R60J106 0603 6.3 Taiyo Yuden X5R JMK107BJ475 0603 6.3 TDK X5R C1608JB0J106K 0603 6.3 Panasonic X5R ECJ1VB0J106M 0603 6.3 The buck regulators require 10 μF output capacitors to guar- antee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications, where one or both buck regulator powers a processor, the operating state is known because it is con- trolled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 μF to 4.7 μF because the regulator does not expect a large load variation when working in PSM mode, see Figure 50. SW1 VIN1 VIN2 EN1 EN2 EN3 VDDA VIN3 VOUT1 PGND1 MODE VOUT3 L1 1µH C4 4.7µF SW2 VOUT2 PGND2 L2 1µH C5 4.7µF C6 1µF C2 4.7µF C3 4.7µF C1 1µF VIN 2.5V TO 5.5V MICRO PMU ADP5022 PROCESSOR ANALOG SUB-SYSTEM VCORE GPIO VIO VANA Figure 50. Processor System Power Management with PSM/PWM Control Input Capacitor Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capa- citor current is calculated using the following equation: IN OUT IN OUT MAX LOAD CIN V V V V I I ) ( ) ( − ≥ To minimize supply noise, place the input capacitor as close to the VIN pin of the BUCK as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 μF and a maximum of 10 μF. A list of suggested capacitors is shown in Table 9. Table 9. Suggested 4.7 μF Capacitors Vendor Type Model Case Size Voltage Rating (V) Murata X5R GRM188R60J475ME19D 0402 6.3 Taiyo Yuden X5R JMK107BJ475 0402 6.3 Panasonic X5R ECJ-0EB0J475M 0402 6.3 LDO CAPACITOR SELECTION Output Capacitor The ADP5022 LDO is designed for operation with small, space- saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5022. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacit- ance improves the transient response of the ADP5022 to large changes in load current. Input Bypass Capacitor Connecting a 1 μF capacitor from VIN3 to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 1 μF of output capacitance is required, increase the input capacitor to match it. Table 10. Suggested 1.0 μF Capacitors Vendor Type Model Case Size Voltage Rating (V) Murata X5R GRM155B30J105K 0402 6.3 TDK X5R C1005JB0J105KT 0402 6.3 Panasonic X5R ECJ0EB0J105K 0402 6.3 Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0 |
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