ExpressLane™ PCI Express to PCI Bridge

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Features

General Features

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Forward and Reverse bridging

1.0 mm pitch (13mm x 13mm)

(10mm x 10mm)

SPI

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1.5 V core supply voltage

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JTAG

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Four (4) GPIO pins for maximum

design flexibility

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Extensive PME support including

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Lead-free packaging available

Integrated PCI Express Interface

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PCI Express Base 1.0a compliant

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x1 Link, dual-simplex, 2.5 Gbps per

direction

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One virtual channel

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Automatic LVDS polarity reversal

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128 byte maximum payload size

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Link CRC

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Link power management

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Flow control buffering

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PCI Express transaction queues for

eight (8) outstanding TLPs

PCI Interface

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PCI v.3.0: 32 bits, up to 66 MHz

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PCI Power Management 1.1

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Internal arbiter supports up to 4

external masters; REQ#/GNT#

signals

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3.3V I/O and 5V tolerant PCI

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Message Signal Interrupt (MSI)

support

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Provides PCI clock output

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Four mailbox registers for messaging

legacy operation

Reversible Bridge in a Tiny Package

The PLX Technology PEX 8111 bridge enables designers to migrate legacy PCI bus

interfaces to the new advanced serial PCI Express. This is ideal for including

existing PCI ICs on a PCI Express™ Adapter Board, such as the new ExpressCard™

or AdvancedMC™ standards. Both the standard BGA package and the tiny 10mm x

10mm fine-pitch package offering make the PEX 8111 bridge well suited for

applications where board real estate is at a premium. With its low power 0.15 micron

CMOS design, the PEX 8111 consumes only about 400 mW of power.

Forward and Reverse Bridging

The PEX 8111 supports forward and reverse bridging as defined by the

PCI Express-to-PCI/PCI-X Bridge Specification 1.0. In forward mode, the bridge

allows legacy PCI chips and adapters to be used with new PCI Express processor

systems. Reverse bridge operation allows conventional PCI processors and chipsets

to configure and control advanced PCI Express switches and endpoints. The reverse

PEX 8111 not only allows complete configuration of a downstream PCI Express

system from the PCI bus, but it also handles limited PCI Express root functions for

reverse interrupt and Power Management Events.

Block Diagram

The PEX 8111 is equipped with a

standard PCI Express port that

operates as a single, x1 link with a

maximum of 250 Megabytes per

second of throughput per transmit

and receive direction. The single 2.5

Gbps integrated SerDes delivers the

highest bandwidth with the lowest

possible pin count using LVDS

technology.

The PEX 8111 has a single parallel

bus segment supporting the PCI v.3.0

protocol, and a 32-bit wide parallel

data path running up to 66MHz.

The device supports internal queues

with flow control features to optimize

throughput and traffic flow.

PEX 8111

Version 1.4 2005

Figure 1. PEX 8111 Block Diagram

j

PCI Express Link (1 lane, 2.5 GHz)

PCI Master and Target Interface Logic

PCI Express Data Link Layer

PCI Express PHY Layer

PCI Express Transaction Layer

(Packet Construction Logic)

FIFOs

8K Shared

RAM

Configuration

Registers

PCI Bus (32-bit, 33/66 MHz)