HT82K74EE datasheet(3/56 Pages) HOLTEK

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Pin Description

Pin Name

I/O

Options

Description

PA0~PA1

PA2/TMR

PA3~PA7

I/O

Pull-high

Wake-up

Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up

input (both falling and rising edge) by a configuration option. Software instruc-

tions determine if the pin is a CMOS output or Schmitt Trigger input. Configura-

tion options determine if the pins have pull-high resistors. PA2 is shared with

the external timer input pin TMR.

PB0~PB7

I/O

Pull-high

Wake-up

Bidirectional 8-bit input/output port. Each nibble, PB0~PB3 and PB4~PB7,

pins can be configured as wake-up inputs (both falling and rising edge) by con-

figuration options. Software instructions determine if the pin is a CMOS output

or Schmitt Trigger input. Configuration options determine if the pins have

pull-high resistors.

PC0~PC7

I/O

Pull-high

Wake-up

Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7,

pins can be configured as wake-up inputs (both falling and rising edge) by con-

figuration options. Software instructions determine if the pin is a CMOS output

or Schmitt Trigger input. Configuration options determine if the pins have

pull-high resistors.

PD0/VA

PD1/VB

PD2/ZA

PD3/ZB

PD4~PD7

I/O

Pull-high

Wake-up

Bidirectional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7,

pins can be configured as wake-up inputs (both falling and rising edge) by con-

figuration options. Software instructions determine if the pin is a CMOS output

or Schmitt Trigger input. Configuration options determine if the pins have

pull-high resistors. PD0 and PD1 are shared with the VA and VB pins. PD2 and

PD3 are shared with the ZA and ZB pins.

PE0~PE3

I/O

Pull-high

Wake-up

Bidirectional 4-bit input/output port. PE0~PE3 pin can be configured as

wake-up inputs (both falling and rising edge) by a configuration option. Soft-

ware instructions determine if the pin is a CMOS output or Schmitt Trigger in-

put. Configuration options determine if the pins have pull-high resistors. For

HT82K74EE PE0 and PE1 are shared with the SDA and SCL lines respec-

tively and not bonded to external pins.

OSC1

OSC2

OSC1, OSC2 are connected to an external 27MHz crystal/ resonator for the in-

ternal system clock.

VSS

¾¾

Negative power supply, ground

RES

Schmitt trigger reset input. Active low

VDD

¾¾

Positive power supply

BAT_IN

Battery input

DC/DC LX switch

VSSLX

DC/DC ground

RF_OUT

Full Power/

Half Power

RF power amplifier output pin

Absolute Maximum Ratings

Supply Voltage ...........................VSS

-0.3V to VSS+6.0V

Storage Temperature ............................

-50°Cto125°C

Input Voltage..............................VSS

-0.3V to VDD+0.3V

Operating Temperature...........................

-40°Cto85°C

IOL Total ..............................................................150mA

IOH Total............................................................

-100mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

HT82K74E/HT82K74EE

Rev. 1.00

December 15, 2009

HT82K74EE 数据表(PDF) 3 Page - Holtek Semiconductor Inc

HT82K74EE 数据表(HTML) 3 Page - Holtek Semiconductor Inc

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HT82K74EE 数据表(PDF) 3 Page - Holtek Semiconductor Inc

HT82K74EE 数据表(HTML) 3 Page - Holtek Semiconductor Inc

Html Pages

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数据表 下载

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