MPC5633MF0MMGA4 datasheet(13/118 Pages) FREESCALE

13 / 118 page

Overview

MPC5634M Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

— e200z335 core complex Instruction port

— e200z335 core complex Load/Store port

—eDMA

•

4 slave ports

—FLASH

— calibration bus

—SRAM

— Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM

and SWT)

•

32-bit internal address, 64-bit internal data paths

1.3.3

eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation

is utilized to minimize the overall block size. The eDMA module provides the following features:

•

All data movement via dual-address transfers: read from source, write to destination

•

Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes

•

Transfer control descriptor organized to support two-deep, nested transfer operations

•

An inner data transfer loop defined by a “minor” byte transfer count

•

An outer data transfer loop defined by a “major” iteration count

•

Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continuous transfers

— Peripheral-paced hardware requests (one per channel)

•

Support for fixed-priority and round-robin channel arbitration

•

Channel completion reported via optional interrupt requests

•

1 interrupt per channel, optionally asserted at completion of major iteration count

•

Error termination interrupts are optionally enabled

•

Support for scatter/gather DMA processing

•

Channel transfers can be suspended by a higher priority channel

1.3.4

Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request

sources, plus 165 sources reserved for compatibility with other family members).

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that

all tasks which share the resource can not preempt each other.

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