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MPC8535EAVTATH 数据表(PDF) 21 Page - Freescale Semiconductor, Inc |
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MPC8535EAVTATH 数据表(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 126 page  Overall DC Electrical Characteristics MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21 2 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2 provides the absolute maximum ratings. 25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No Connect” or terminated through 2–10 K Ω pull-up resistors with the default of internal arbiter if the address pins are not connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 26.MDIC[0] is grounded through an 18.2- Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor and MDIC[1] is connected to GVDD through an 18.2- Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 27.Connect to GND through a pull down 1 k Ω resistor. 28. It must be the same as VDD_CORE 29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when GCR[DEEPSLEEP_Z] =1. 30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC™ III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller operation in asynchronous and synchronous modes. 31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND. 32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for SD/MMC card specification. 33. Must connect to XGND. 34. Must connect to X2GND Table 2. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD_CORE –0.3 to 1.21 V — Platform supply voltage VDD_PLAT –0.3 to 1.1 V — PLL core supply voltage AVDD_CORE –0.3 to 1.21 V — PLL other supply voltage AVDD –0.3 to 1.1 V — Core power supply for SerDes transceivers SVDD, S2VDD –0.3 to 1.1 V — Pad power supply for SerDes transceivers and PCI Express XVDD, X2VDD –0.3 to 1.1 V — Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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