ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

7

Day digit register ( at internal address 4H )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

-

-

D20

D10

D8

D4

D2

D1

Write

0

0

D20

D10

D8

D4

D2

D1

Read

0

0

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Default

*Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

Mouth digit register ( at internal address 5H )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

-

-

-

MO10

MO8

MO4

MO2

MO1

Write

0

0

0

MO10

MO8

MO4

MO4

MO1

Read

0

0

0

Undefined

Undefined

Undefined

Undefined

Undefined

Default

*Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

Year digit register ( at internal address 6H )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

Write

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

Read

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Default

*Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

4. Time Trimming Register ( at internal address 7H )

D7

D6 D5 D4 D3 D2 D1 D0 Operation

XSL_

F6

F5

F4

F3

F2

F1

F0

Write

XSL_

F6

F5

F4

F3

F2

F1

F0

Read

0

0

0

0

0

0

0

0

Default

*Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

XSL bit

The

⎯XSL bit is used to select a crystal oscillator.Set the ⎯XSL to“0”(default) to use 32.768KHz；Set ⎯XSL

to“1”to use 32KHz.

F6 to F0

The time trimming circuit adjust one second count based on this readings when second digit is 00,20, or

40 seconds. Normally, counting up to seconds is made once per 32,768 of clock pulse (or 32,000 when

32.000KHz crystal is used) generated by the oscillator. Setting data to this register activates the time

trimming circuit. Register counts will be incremented as (( F5,F4,F3,F2,F1,F0)-1) x2 when F6 is set to “0”.

Register counts will be incremented as ((F5, F4, F3, F2, F1, F0)-1) x2 when F6 is set to “0”.

Register counts will be decremented as ((

⎯F5, ⎯F4, ⎯F3, ⎯F2, ⎯F1, ⎯F0)+1) x2 when F6 is set to “1”.

Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (*, 0, 0, 0, 0, 0, *).