ACE5372

Low Power Real-Time Clock (RTC)

VER 1.2

16

When the transmission direction is to be changed during transmission

Data Transmission Write Format in the ACE5372

A) First send 7 address bit(0110010), the eighth bit is write command “0”.

B) When the ninth bit is ACK signal, ACE5372 is under writing condition.

C)In the following byte, the high 4 bits are determined as internal address in ACE5372(0H-FH), the low 4

bits are transmission model.

D)After another bit’s ACK signal, it starts writing data normally.

E)After writing 1 byte data, there will be 1 bit ACK signal and then writing data in next 1 byte starts. Only

when there is a stop signal in the bit after ACK signal, can the writing operation be stopped.

Example of data writing (When writing to internal address 4H to 5H)

Data Transmission Read Format in the ACE5372

The ACE5372 allows the following three readout methods of data from an internal register.

I) The first method to reading data from the named internal address

A)The first three steps are the same as write model

B)After one bit ACK signal, a new start signal will be produced to change the direction of data

transmission in INTERFACE connection.

C)Then send 7 address bit(0110010), the eighth bit command is “1”, ACE5372 is under data reading

condition.

D) After another bit’s ACK signal, it starts reading data normally.

CPU to ACE5372

ACE5372 to CPU

Acknowledge signal

Start condition

Stop condition