ADE7878ACPZ datasheet(59/92 Pages) AD

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ADE7878

Rev. 0 | Page 59 of 92

Sign of Sum-of-Phase Powers in the CFx Datapath

The ADE7878 has a sign detection circuitry for the sum of

phase powers that are used in the CFx datapath. As seen in the

beginning of the Energy-to-Frequency Conversion section, the

energy accumulation in the CFx datapath is executed in two

stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is, after the

energy accumulated into the 55-bit accumulator reaches one

of WTHR[47:0], VARTHR[47:0], or VATHR[47:0] thresholds,

a dedicated interrupt may be triggered synchronously with the

corresponding CFx pulse. The sign of each sum can be read in

the PHSIGN[15:0] register.

Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and

REVPSUM1, respectively) of the STATUS0[31:0] register are set

to 1 when a sign change of the sum of powers in CF3, CF2, or

CF1 datapaths occurs. To correlate these events with the pulses

generated at the CFx pins, after a sign change occurs, Bit

REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set in

the same moment in which a high-to-low transition at the CF3,

CF2, and CF1 pin, respectively, occurs.

Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and

SUM1SIGN, respectively) of the PHSIGN[15:0] register are set

in the same moment with Bit REVPSUM3, Bit REVPSUM2, and

Bit EVPSUM1 and indicate the sign of the sum of phase powers.

When cleared to 0, the sum is positive. When set to 1, the sum

is negative.

Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,

REVPSUM2, and REVPSUM1, respectively) in the STATUS0[31:0]

MASK0[31:0] register. If enabled, the IRQ0 pin is set low and

the status bit is set to 1 whenever a change of sign occurs. To

find the phase that triggered the interrupt, the PHSIGN[15:0]

high again by writing to the STATUS0 register with the

corresponding bit set to 1.

NO LOAD CONDITION

The no load condition is defined in metering equipment

standards as occurring when the voltage is applied to the meter

and no current flows in the current circuit. To eliminate any

creep effects in the meter, the ADE7878 contains three separate

no load detection circuits: one related to the total active and

reactive powers, one related to the fundamental active and

reactive powers, and one related to the apparent powers.

No Load Detection Based On Total Active, Reactive

Powers

This no load condition is triggered when the absolute values of

both phase total active and reactive powers are less than or

equal to positive thresholds indicated in the APNOLOAD[23:0]

and respective VARNOLOAD[23:0] signed 24-bit registers. In

this case, the total active and reactive energies of that phase are

not accumulated, and no CFx pulses are generated based on

these energies. The APNOLOAD[23:0] register represents the

positive no load level of active power relative to PMAX, the

maximum active power obtained when full-scale voltages and

currents are provided at ADC inputs. The VARNOLOAD[23:0]

relative to PMAX. The expression used to compute

APNOLOAD[23:0] signed 24-bit value is

PMAX

APNOLOAD

NOLOAD

(47)

where:

PMAX = 3,516,139 = 0x1FF6A6B, the instantaneous power

computed when the ADC inputs are at full scale.

UFS, IFS are the rms values of the phase voltages and currents

when the ADC inputs are at full scale.

Un is the nominal rms value of phase voltage.

INOLOAD is the minimum rms value of phase current the meter

starts measuring.

The VARNOLOAD[23:0] register usually contains the same

value as the APNOLOAD[23:0] register. When APNOLOAD

and VARNOLOAD are set to negative values, the no load

detection circuit is disabled.

As previously stated, the serial ports of the ADE7878 work on

32-, 16-, or 8-bit words, and the DSP works on 28 bits. the

APNOLOAD and VARNOLOAD 24-bit signed registers are

accessed as 32-bit registers with the four MSBs padded with 0s

and sign extended to 28 bits. See Figure 32 for details.

Bit 0 (NLOAD) in the STATUS1[31:0] register is set when this

no load condition in one of the three phases is triggered.

Bits[2:0] (NLPHASE[2:0]) in the PHNOLOAD[15:0] register

indicate the state of all phases relative to a no load condition

and are set simultaneously with Bit NLOAD in the

STATUS1[31:0] register. NLPHASE[0] indicates the state of

Phase A, NLPHASE[1] indicates the state of Phase B, and

NLPHASE[2] indicates the state of Phase C. When Bit

NLPHASE[x] is cleared to 0, it means that the phase is out of a

no load condition. When set to 1, it means that the phase is in a

no load condition.

An interrupt attached to Bit 0 (NLOAD) in the STATUS1[31:0]

is set to 1 whenever one of three phases enters or exits this no

load condition. To find the phase that triggered the interrupt,

the PHNOLOAD[15:0] register is read immediately after

reading the STATUS1[31:0] register. Then, the status bit is

cleared and the IRQ1 pin is set to high by writing to the

STATUS1 register with the corresponding bit set to 1.

ADE7878ACPZ 数据表(PDF) 59 Page - Analog Devices

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