ADE7878ACPZ datasheet(62/92 Pages) AD

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ADE7878

Rev. 0 | Page 62 of 92

INTERRUPTS

The ADE7878 has two interrupt pins, IRQ0 and IRQ1. Each of the

pins is managed by a 32-bit interrupt mask register, MASK0[31:0]

and MASK1[31:0], respectively. To enable an interrupt, a bit in

the MASKx[31:0] register must be set to 1. To disable it, the bit

must be cleared to 0. Two 32-bit status registers, STATUS0[31:0]

and STATUS1[31:0], are associated with the interrupts. When

an interrupt event occurs in the ADE7878, the corresponding

flag in the interrupt status register is set to a Logic 1 (see

and

). If the mask bit for this interrupt in the interrupt

mask register is Logic 1, then the

Table 31

Table 32

IRQx logic output goes active

low. The flag bits in the interrupt status register are set irrespective

of the state of the mask bits. To determine the source of the

interrupt, the MCU should perform a read of the corresponding

STATUSx register and identify which bit is set to 1. To erase the

flag in the status register, STATUSx should be written back with

the flag set to 1. After an interrupt pin goes low, the status register

is read and the source of the interrupt is identified. Then, the

status register is written back without any change to clear the

status flag to 0. TheIRQx pin remains low until the status flag is

cancelled.

By default, all interrupts are disabled. However, the RSTDONE

interrupt is an exception. This interrupt can never be masked

(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1[31:0]

goes low and Bit 15 (RSTDONE) in the STATUS1[31:0] is set to

1 whenever a power-up or a hardware/software reset process ends.

To cancel the status flag, the STATUS1[31:0] register must be

written with Bit 15 (RSTDONE) set to 1.

Certain interrupts are used in conjunction with other status

registers: Bit 0 (NLOAD), Bit1 (FNLOAD), and Bit 2 (VANLOAD)

in the MASK1[31:0] register work in conjunction with status

bits in the PHNOLAD[15:0] register. Bit 16, (sag), Bit 17 (OI),

and Bit 18 (OV) in the MASK1[31:0] register work with status

bits in the PHSTATUS[15:0] register. Bit 23 (PKI) and Bit 24

(PKV) in the MASK1[31:0] register work with status bits in

the IPEAK[31:0] and VPEAK[31:0], respectively. Bits[6:8]

(REVAPx), Bits[10:12] (REVRPx), and Bit 9, Bit 13, and Bit 18

(REVPSUMx) in the MASK0[31:0] register work with the status

bits in the PHSIGN[15:0] register. When the STATUSx[31:0]

the phase that triggered the interrupt, and only at that time can

the STATUSx[31:0] register be written back with the bit set to 1.

Using the Interrupts with an MCU

Figure 78 shows a timing diagram that illustrates a suggested

implementation of the ADE7878 interrupt management using

an MCU. At Time t1, the IRQx pin goes active low indicating

that one or more interrupt events occurred in the ADE7878. Tie

the IRQx pin to a negative-edge-triggered external interrupt on

the MCU. On detection of the negative edge, configure the

MCU to start executing its interrupt service routine (ISR). On

entering the ISR, disable all interrupts using the global interrupt

mask bit. At this point, the MCU external interrupt flag can be

cleared to capture interrupt events that occur during the current

ISR. When the MCU interrupt flag is cleared, a read from

STATUSx, the interrupt status register, is carried out. The

interrupt status register content is used to determine the source

of the interrupt(s) and, hence, the appropriate action to be

taken. Next, the same STATUSx content is written back into the

ADE7878 to clear the status flag(s) and reset the IRQx line to

logic high (t2). If a subsequent interrupt event occurs during the

ISR (t3), that event is recorded by the MCU external interrupt

flag being set again.

On returning from the ISR, the global interrupt mask bit is

cleared (same instruction cycle), and the external interrupt flag

uses the MCU to jump to its ISR once again. This ensures that

the MCU does not miss any external interrupts.

Figure 79 shows a recommended timing diagram when the

status bits in the STATUSx registers work in conjunction with

bits in other registers. Same as previously described, when the

IRQx pin goes active low, the STATUSx register is read and if

one of these bits is 1, then a second status register is read

immediately to identify the phase that triggered the interrupt.

The name, PHx, in

denotes one of the PHSTATUS,

IPEAK, VPEAK, or PHSIGN registers. Then, STATUSx is

written back to clear the status flag(s).

Figure 79

JUMP

TO ISR

GLOBAL

INTERRUPT

MASK

CLEAR MCU

INTERRUPT

FLAG

READ

STATUSx

JUMP

TO ISR

WRITE

BACK

STATUSx

ISR ACTION

(BASED ON STATUSx CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

MCU

INTERRUPT

FLAG SET

PROGRAM

SEQUENCE

IRQx

Figure 78. Interrupt Management

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