CHA2092b

18-32GHz Low Noise Amplifier

Ref. : DSCHA20921233 21-August-01

6/6

Specifications subject to change without notice

Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE

Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09

Typical Bias Tuning

The circuit schematic is given below :

IN

OUT

Vd 1,2,3

Vg 2,3

Vg 1

The three drain biases are connected altogether on chip. For typical operation, all the gate

biases are connected together at the same power supply, tuned to drive a small signal

operating current of 60 mA. A separate access to the gate voltages of the first stage ( Vg1 )

and the second and third stages ( Vgs2,3 ) is provided for the fine tuning of the amplifier

regarding the application.

Ordering Information

Chip form

:

CHA2092b99F/00

Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors

S.A.S. assumes no responsability for the consequences of use of such information nor for any infringement of

patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use

as critical components in life support devices or systems without express written approval from United

Monolithic Semiconductors S.A.S.