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AS1536/AS1537

Datasheet - D e t a i l e d D e s c r i p t i o n

The devices’ input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize

high-speed transient events) and measure periodic signals with bandwidths exceeding the devices’ sampling rate.

Note: Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of

interest.

Input Protection

more than 50mV, or be lower than GND by 50mV.

Note: If the analog input exceeds the supply by 50mV, limit the input current to 2mA.

Track/Hold

In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog

the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the

to the input signal again.

(EQ 1)

Where:

Ω

Ω do not significantly affect the AC performance of the devices.

Note: Higher source impedances can be used if a 0.01µF capacitor is connected to the analog input. Note that the

input capacitor forms an RC filter with the input source impedance, limiting the devices’ input signal bandwidth.

External Clock

The AS1536/AS1537 do not require an external clock for analog-to-digital data conversion. This allows the micropro-

cessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is

unrestricted if each clock phase is at least 200ns.

Note: The external clock must not be run while a conversion is in progress.

Timing and Control

Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures 25 - 27

(see page 14) for graphical timing and control information.

The falling edge on pin CSN initiates a conversion sequence:

1. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins.

2. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion.

3. The internal SAR stores the data during the conversion process.

4. Pin DOUT going high indicates the conversion process has completed.

5. The rising edge of pin DOUT can be used as a framing signal.

6. SCLK shifts the data out of this register any time after the conversion is complete.

7. DOUT transitions on the falling edge of pin SCLK.

8. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since

there are 12 data bits and one leading high-bit 13 falling clock edges are needed to shift out these bits, respectively.