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Revision 1.01

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AS1536/AS1537

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Figure 33. Microwire Serial Interface Connections

A conversion process begins on the falling edge of CSN (see Figure 34). DOUT goes low, indicating a conversion is in

progress. Wait until DOUT goes high or until the maximum specified conversion time elapses before starting another

conversion. Two consecutive 1-byte reads are required to retrieve the full 12 bits from the devices.

Output data transitions occurs on the falling edge of SCLK, and is clocked into the microprocessor on the rising edge of

SCLK. The first byte contains a leading 1, and seven bits of conversion result data. The second byte contains the

remaining five bits of conversion result data, and three trailing zeros.

Figure 34. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)

QSPI

When interfacing the AS1536/AS1537 to a microprocessor’s QSPI interface (see Figure 35), set QSPI control register

CPOL = CPHA = 0.

Figure 35. QSPI Serial Interface Connections

AS1536/

AS1537

CPU

SI

I/O

SK

6

DOUT

7

CSN

8

SCLK

1st Byte Read

2nd Byte Read

LSB

MSB

EOC

CSN

SCLK

DOUT

D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

High-Z

when CSN

is High

AS1536/

AS1537

CPU

SSM

MISO

CSM

SCK

6

DOUT

7

CSN

8

SCLK