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AS1543/44

Data Sheet - D e t a i l e d D e s c r i p t i o n

The CSN signal initiates the data transfer and conversion process. The falling edge of CSN puts the track and hold into

hold mode, takes the bus out of three-state, and the analog input is sampled at this point. The conversion is also initi-

ated at this point and will require 16 SCLK cycles to complete.

The track and hold will go back into track on the 14th SCLK falling edge (point B in Figure 31) except when the write is

to the shadow register, in which case the track and hold will not return to track until the rising edge of CSN, (point C in

Figure 32).

On the 16th SCLK falling edge, signal DOUT will go back into tri-state (assuming bit WEAK/TRIN (page 14) is set to 0).

Sixteen serial clock cycles are required to perform the conversion process and to access data from the AS1543/44.

The 12 bits of data are preceded by the four channel address bits ADDR3:ADDR0 (page 14), identifying which channel

the conversion result corresponds to.

CSN going low provides address bit ADDR3 to be read in by the microprocessor or DSP. The remaining address bits

and data bits are then clocked out by subsequent SCLK falling edges beginning with the second address bit ADDR2;

thus the first SCLK falling edge on the serial clock has address bit ADDR3 provided and also clocks out address bit

ADDR2. The final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous

(15th) falling edge.

Figure 32. Shadow Register Write Operation Timing Diagram, AS1543

Writing information to the control register takes place on the first 13 falling edges of SCLK in a data transfer, assuming

the MSB, i.e., bit WRITE (page 14), has been set to 1. If the control register is programmed to use the shadow register,

writing of information to the shadow register will take place on all 16 SCLK falling edges in the next serial transfer (see

Figure 32). The shadow register will be updated upon the rising edge of CSN and the track and hold will begin to track

the first channel selected in the sequence.

the programming of the shadow register. CSN will then go high after the 17th clock. In all other cases, 16

clocks will be enough to program the shadow register.

If bit WEAK/TRIN (page 14) is set to 1, rather than returning to true tri-state upon the 16th SCLK falling edge, the

DOUT signal will instead be pulled weakly to the logic level corresponding to bit ADDR3 of the next serial transfer. This

is done to ensure that the MSB of the next serial transfer is set up in time for the first SCLK falling edge after the CSN

falling edge.

If bit WEAK/TRIN is set to 0 and the DOUT signal has been in true tri-state between conversions, then depending on

the particular DSP or microcontroller interfacing to the AS1543/44, address bit ADDR3 may not be set up in time for

the DSP/micro to clock it in successfully. In this case, ADDR3 would only be driven from the falling edge of CSN and

must then be clocked in by the DSP on the following falling edge of SCLK.

2

5

4

3

6

13

14

1

15

16

DB2

DB1

DB0

C

DB10

DB11

ADDR0

ADDR1

ADDR2

Tri-State

SCLK

CSN

DOUT

DIN

Tri-State

ADDR3

4 ID Bits