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AS3930

Data Sheet - D e t a i l e d D e s c r i p t i o n

8.2.4 Data Receiving

The user can enable this mode allowing the pattern correlation or just on the base of the frequency detection. In this mode the chip can be

retained as a normal OOK receiver. The data is provided on the DAT pin and in case the Manchester decoder is enabled see R1<3>, the

recovered clock is present on the CL_DAT. It is possible to put the chip back to listening mode either with a direct command (CLEAR_WAKE (see

Table 12)) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time defined in the

R7<7:5>

.

8.3 System and Block Specification

8.3.1 Main Logic and SDI

8.3.1.1 Register Table

8.3.1.2 Register Table Description and Default Values

Table 6. Register Table

7

6

5

4

3

2

1

0

R0

n.a.

ON_OFF

Reserved

EN_A

PWD

R1

ABS_HY

AGC_TLIM

AGC_UD

ATT_ON

EN_MANCH

EN_PAT2

EN_WPAT

EN_RTC

R2

S_ABSH

W_PAT_T<1:0>

Reserved

S_WU1<1:0>

R3

HY_20m

HY_POS

FS_SLC<2:0>

FS_ENV<2:0>

R4

T_OFF<1:0>

R_VAL<1:0>

GR<3:0>

R5

TS2<7:0>

R6

TS1<7:0>

R7

T_OUT<2:0>

T_HBIT<4:0>

R8

n.a.

T_AUTO<2:0>

R9

n.a.

Reserved

R10

n.a.

RSSI1<4:0>

R11

n.a.

RSSI3<4:0>

R12

n.a.

RSSI2<4:0>

R13

F_WAKE

Table 7. Default Values of Registers

Register

Name

Type

Default

Value

Description

R0<5>

ON_OFF

W

0

On/Off operation mode. (Duty-cycle defined in the register R4<7:6>)

R0<4>

MUX_123

W

0

Reserved (it is not allowed to set this bit to 1)

R0<3>

Reserved

W

1

Reserved

R0<2>

Reserved

W

1

Reserved

R0<1>

EN_A

W

1

Channel enable

R0<0>

PWD

W

0

Power down

R1<7>

ABS_HY

W

0

Data slicer absolute reference

R1<6>

AGC_TLIM

W

0

AGC acting only on the first carrier burst

R1<5>

AGC_UD

W

1

AGC operating in both direction (up-down)

R1<4>

ATT_ON

W

0

Antenna damper enable

R1<3>

EN_MANCH

W

0

Manchester decoder enable