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AS3930

Data Sheet - D e t a i l e d D e s c r i p t i o n

If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not

be longer than 40 bits (see bit rate definition in Table 18). The data pattern can be defined by the user and consists of two bytes which are stored

in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit

period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and

timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down

represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first.

The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern

has to be repeated 2 times.

Additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the Table

19.

If the pattern is matched the wake-up interrupt is displayed on the WAKE output. In case the Manchester decoder is enabled (R1<3>) the data

coming out from the DAT pin are decoded and the clock is recovered on the pin DAT_CL.

The data coming out from the DAT pin are stable (and therefore can be acquired) on the rising edge of the CL_DAT clock, as shown in Figure 16.

0

1

1

1

0

15

2184

1092

0

1

1

1

1

16

2048

1024

1

0

0

0

0

17

1926

963

1

0

0

0

1

18

1820

910

1

0

0

1

0

19

1724

862

1

0

0

1

1

20

1638

819

1

0

1

0

0

21

1560

780

1

0

1

0

1

22

1488

744

1

0

1

1

0

23

1424

712

1

0

1

1

1

24

1364

682

1

1

0

0

0

25

1310

655

1

1

0

0

1

26

1260

630

1

1

0

1

0

27

1212

606

1

1

0

1

1

28

1170

585

1

1

1

0

0

29

1128

564

1

1

1

0

1

30

1092

546

1

1

1

1

0

31

1056

528

1

1

1

1

1

32

1024

512

Table 19. Allowed Pattern Detection Errors

R2<6>

R2<5>

Maximum allowed error in the pattern detection

0

0

No error allowed

0

1

1 missed zero

1

0

2 missed zeros

1

1

3 missed zeros

Table 18. Bit Rate Setup

R7<4>

R7<3>

R7<2>

R7<1>

R7<0>

Bit duration in RTC

clock periods

Bit rate (bits/s)

Symbol rate (Manchester

symbols/s)