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AS5040ASST 数据表(PDF) 16 Page - ams AG |
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AS5040ASST 数据表(HTML) 16 Page - ams AG |
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16 / 33 page ![]() AS5040 Data Sheet www.austriamicrosystems.com Revision 2.10 16 - 33 Figure 12: U, V and V-signals for BLDC Motor Commutation (Div1=0, Div0=0) Commutation - Mode 3.0 (One-pole-pair) U V W Position: 0 171 341 512 683 853 0 Angle: 0.0 60.12 119.88 180.0 240.12 299.88 360.0 Width: 512 Steps Width: 512 Steps CW Direction Figure 13: U, V and W-signals for 2-pole BLDC Motor Commutation (Div1=1; Div0=0) Commutation - Mode 3.2 (Two-pole-pairs) U V W Position: 0 85 171 256 341 427 512 597 683 768 853 939 0 Angle: 0.0 29.88 60.12 90.0 119.88 150.12 180.0 209.88 240.12 270.00 299.88 330.12 360.0 Width: 256 Steps Width: 256 Steps CW Direction 12 Programming the AS5040 After power-on, programming the AS5040 is enabled with the rising edge of CSn with Prog = high and CLK = low. 16 bit configuration data must be serially shifted into the OTP register via the Prog-pin. The first “CCW” bit is followed by the zero position data (MSB first) and the incremental mode setting as shown in Table 6. Data must be valid at the rising edge of CLK (see Figure 14). After writing data into the OTP register it can be permanently programmed by rising the Prog pin to the programming voltage VPROG. 16 CLK pulses (tPROG) must be applied to program the fuses (Figure 15). To exit the programming mode, the chip must be reset by a power-on-reset. The programmed data is available after the next power-up. Note: During the programming process, the transitions in the programming current may cause high voltage spikes generated by the inductance of the connection cable. To avoid these spikes and possible damage to the IC, the connection wires, especially the signals Prog and VSS must be kept as short as possible. The maximum wire length between the VPROG switching transistor and pin Prog (see Figure 16) should not exceed 50mm (2 inches). To suppress eventual voltage spikes, a 10nF ceramic capacitor should be connected close to pins Prog and VSS. This capacitor is only required for programming, it is not required for normal operation. The clock timing tclk must be selected at a proper rate to ensure that the signal Prog is stable at the rising edge of CLK (see Figure 14). Additionally, the programming supply voltage should be buffered with a 10µF capacitor mounted close to the switching transistor. This capacitor aids in providing peak currents during programming. The specified programming voltage at pin Prog is 7.3 – 7.5V (see section 0). To compensate for the voltage drop across the VPROG switching transistor, the applied programming voltage may be set slightly higher (7.5 - 8.0V, see Figure 16). |
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