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AS5140H

Data Sheet - D e t a i l e d D e s c r i p t i o n

7.6.7 Zero Position Programming

Zero position programming is an OTP option that simplifies assembly of a system, as the magnet does not need to be manually adjusted to the

mechanical zero position. Once the assembly is completed, the mechanical and electrical zero positions can be matched by software. Any

position within a full turn can be defined as the permanent new zero/index position. For zero position programming, the magnet is turned to the

mechanical zero position (e.g. the “off”-position of a rotary switch) and the actual angular value is read.

7.7 Alignment Mode

The alignment mode simplifies centering the magnet over the center of the chip to gain maximum accuracy. Alignment mode can be enabled with

the falling edge of CSn while Prog = logic high (see Figure 16). The Data bits D9-D0 of the SSI change to a 10-bit displacement amplitude

output. A high value indicates large X or Y displacement, but also higher absolute magnetic field strength. The magnet is properly aligned, when

the difference between highest and lowest value over one full turn is at a minimum. Under normal conditions, a properly aligned magnet will

result in a reading of less than 128 over a full turn. The MagINCn and MagDECn indicators will be = 1 when the alignment mode reading is < 128.

At the same time, both hardware pins MagINCn (#1) and MagDECn (#2) will be pulled to VSS. A properly aligned magnet will therefore produce

a MagINCn = MagDECn = 1 signal throughout a full 360º turn of the magnet. Stronger magnets or short gaps between magnet and IC may show

values larger than 128. These magnets are still properly aligned as long as the difference between highest and lowest value over one full turn is

at a minimum. The Alignment mode can be reset to normal operation by a power-on-reset (disconnect / re-connect power supply) or by a falling

edge on CSn with Prog = low.

Table 20. One Time Programmable (OTP) Register Options

Mode

OTP-Mode-Register-Bit

Pin#

Pulses per

Revolution

Incremental

Resolution

Md1 Md0 Div1 Div0 Index

3

4

6

12

ppr

bit

Default (Mode0.0)

1

1. Div1, Div0 and Index cannot be programmed in Mode 0:0

00

0

0

0

AB

1LSB

PWM

10 bit

2 x 256

10

quadAB-Mode1.0

0

1

0

0

0

1LSB

quadAB-Mode1.1

0

1

0

0

1

3LSBs

quadAB-Mode1.2

0

1

0

1

0

1LSB

2 x 128

9

quadAB-Mode1.3

0

1

0

1

1

3LSBs

quadAB-Mode1.4

0

1

1

0

0

1LSB

2 x 64

8

quadAB-Mode1.5

0

1

1

0

1

3LSBs

quadAB-Mode1.6

0

1

1

1

0

1LSB

2 x 32

7

quadAB-Mode1.7

0

1

1

1

1

3LSBs

Step/Dir-Mode2.0

1

0

0

0

0

LSB

Dir

1LSB

PWM

10 bit

512

10

Step/Dir-Mode2.1

1

0

0

0

1

3LSBs

Step/Dir -Mode2.2

1

0

0

1

0

1LSB

256

9

Step/Dir -Mode2.3

1

0

0

1

1

3LSBs

Step/Dir -Mode2.4

1

0

1

0

0

1LSB

128

8

Step/Dir -Mode2.5

1

0

1

0

1

3LSBs

Step/Dir -Mode2.6

1

0

1

1

0

1LSB

64

7

Step/Dir -Mode2.7

1

0

1

1

1

3LSBs

Commutation-Mode3.0

1

1

0

0

0

U(0º) V(120º)

W(240º)

LSB

3 x 1

10

Commutation-Mode3.1

1

1

0

1

0

9

Commutation-Mode3.2

1

1

1

0

0

U’

(0º,18

0º)

V’

(60º,240º

)

W’

(120º,300º) LSB

2 x 3

10

Commutation-Mode3.3

1

1

1

1

0

9