MCP6281-ESLASHMS datasheet(12/36 Pages) MICROCHIP

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MCP6281/1R/2/3/4/5

DS21811E-page 12

4.0

APPLICATION INFORMATION

The MCP6281/1R/2/3/4/5 family of op amps is manu-

factured using Microchip's state-of-the-art CMOS

process. This family is specifically designed for low-

cost, low-power and general purpose applications.

The low supply voltage, low quiescent current and

wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal

for battery-powered applications.

4.1

Rail-to-Rail Inputs

4.1.1

PHASE REVERSAL

The MCP6281/1R/2/3/4/5 op amp is designed to

prevent phase reversal when the input pins exceed the

supply voltages. Figure 2-32 shows the input voltage

exceeding the supply voltage without any phase

reversal.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

FIGURE 4-1:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these op amps, the circuit they are in must limit the

currents and voltages at the VIN+ and VIN– pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-2

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(VIN+ and VIN–) from going too far below ground, and

the resistors R1 and R2 limit the possible current drawn

out of the input pins. Diodes D1 and D2 prevent the

input pins (VIN+ and VIN–) from going too far above

VDD, and dump any currents onto VDD. When

implemented as shown, resistors R1 and R2 also limit

the current through D1 and D2.

FIGURE 4-2:

Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of

resistors R1 and R2. In this case, current through the

diodes D1 and D2 needs to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN–) should be very small.

A significant amount of current can flow out of the

inputs when the common mode voltage (VCM) is below

ground (VSS); see Figure 2-31. Applications that are

high impedance may need to limit the usable voltage

range.

4.1.3

NORMAL OPERATION

The input stage of the MCP6281/1R/2/3/4/5 op amps

use two differential CMOS input stages in parallel. One

operates at low common mode input voltage (VCM),

while the other operates at high VCM. WIth this

topology, the device operates with VCM up to 0.3V

above VDD and 0.3V below VSS.

There is a transition in input behavior as VCM is

changed. It occurs when VCM is near VDD –1.2V (see

Figure 2-3 and Figure 2-6). For the best distortion

performance with non-inverting gains, avoid these

regions of operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

MCP628X

VDD

R1 >

VSS – (minimum expected V1)

2mA

R2 >

VSS – (minimum expected V2)

2mA

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