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DM9102DEP 数据表(PDF) 39 Page - Davicom Semiconductor, Inc.

部件名 DM9102DEP
功能描述  Single Chip Fast Ethernet NIC Controller
PDF  70 Pages
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制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.

DM9102DEP 数据表(HTML) 39 Page - Davicom Semiconductor, Inc.

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Final
39
Version: DM9102D-DS-F01
May 10, 2006
b3 b2 b1 b0
00
0
0
In IDLE state
00
0
0
Ability match
00
1
0
Acknowledge match
00
1
1
Acknowledge match fail
0
1
0
0
Consistency match
0
1
0
1
Consistency match fail
01
1
0
Parallel detects signal_link_ready
01
1
1
Parallel detects signal_link_ready
fail
10
0
0
Auto-negotiation completed
successfully
6.3.10 10BASE-T Configuration/Status (10BTCSRCSR) – 12H
Bit
Name
Default
Description
15
Reserved
0, RO
Reserved:
Write as 0, ignore on read
14
LP_EN
1, RW
Link Pulse Enable:
1=Transmission of link pulses enabled
0=Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation.
13
HBE
1,RW
Heartbeat Enable:
1=Heartbeat function enabled
0=Heartbeat function disabled
When the DM9102D is configured for Full Duplex operation, this bit will be
ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must
set to be 1.
12
SQUELCH
1, RW
Squelch Enable
1 = normal squelch
0 = low squelch
11
JABEN
1, RW
Jabber Enable:
Enables or disables the Jabber function when the DM9102D is in 10BASE-T
Full Duplex or 10BASE-T Transceiver Loopback mode
1= Jabber function enabled
0= Jabber function disabled
10
Reserved
0,RW
Reserved
9:2
Reserved
0, RO
Reserved
1
Reserved
0,RW
Reserved
0
POLR
0, RO
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed.



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