DM9102DEP datasheet(2/70 Pages) DAVICOM

2 / 70 page

DM9102D

Single Chip Fast Ethernet NIC Controller

Final

Version: DM9102D-DS-F01

May 10, 2006

Table of Contents

1. General Description.............................................................1

2. Block Diagram......................................................................3

3. Features................................................................................4

4 Pin Configuration: DM9102D 128pin LQFP......................5

5. Pin Description...................................................................6

5.1 PCI Bus Interface Signals.................................................6

5.2 Boot ROM and EEPROM Interfaces..............................7

5.3 LED Pins.............................................................................8

5.4 Network Interface ..............................................................8

5.5 Miscellaneous Pins............................................................8

5.6 Power Pins.........................................................................9

5.7 NC Pins.............................................................................10

5.8 strap Pins..........................................................................10

6. Register Definition...........................................................11

6.1 PCI Configuration Registers...........................................11

6.1.1 Identification ID .............................................................12

6.1.2 Command & Status .....................................................13

6.1.3 Revision ID....................................................................14

6.1.4 Miscellaneous Function...............................................15

6.1.5 I/O Base Address.........................................................15

6.1.6 Memory Mapped Base Address................................16

6.1.7 Subsystem Identification..............................................16

6.1.8 Expansion ROM Base Address.................................17

6.1.9 Capabilities Pointer ......................................................17

6.1.10 Interrupt & Latency Configuration.............................18

6.1.11 Device Specific Configuration Register...................18

6.1.12 Power Management Register ..................................19

6.1.13 Power Management Control/Status ........................20

6.2 Control and Status Register (CR)..................................21

6.2.1 System Control Register (CR0)..................................22

6.2.2 Transmit Descriptor Poll Demand (CR1)...................22

6.2.3 Receive Descriptor Poll Demand (CR2) ...................22

6.2.4 Receive Descriptor Base Address (CR3)..................23

6.2.5 Transmit Descriptor Base Address (CR4).................23

6.2.6 Network Status Report Register (CR5) .....................23

6.2.7 Network Operation Register (CR6)............................25

6.2.8 Interrupt Mask Register (CR7)....................................27

6.2.9 Statistical Counter Register (CR8) .............................28

6.2.10 Management Access Register (CR9) .....................29

6.2.11 PHY Status Register (CR12)....................................30

6.2.12 Sample Frame Access Register (CR13) ................30

6.2.13 Sample Frame Data Register (CR14).....................31

6.2.14 Watchdog and Jabber Timer Register (CR15) ......31

6.3 PHY Management Register Set....................................32

6.3.1 Basic Mode Control Register (BMCR)

- Register 0 .............................................................................33

6.3.2 Basic Mode Status Register (BMSR)

- Register 1 .............................................................................34

6.3.3 PHY Identifier Register #1 (PHYIDR1)

- Register 2 .............................................................................35

6.3.4 PHY Identifier Register #2 (PHYIDR2)

- Register 3 .............................................................................35

6.3.5 Auto-negotiation Advertisement Register (ANAR)

- Register 4 .............................................................................35

6.3.6 Auto-negotiation Link Partner Ability Register

(ANLPAR)

- Register 5....................................................36

6.3.7 Auto-negotiation Expansion Register (ANER)

- Register 6 .............................................................................37

6.3.8 DAVICOM Specified Configuration Register (DSCR)

- Register 10H ........................................................................37

6.3.9 DAVICOM Specified Configuration and Status

6.3.10 10Base-T Configuration/Status (10BTSCRCSR)

- Register 12H ........................................................................39

6.3.11 Power Down Control Register (PWDOR)

- Register 13H ........................................................................40

6.3.12 HP Auto-MDIX ControlRegister (MDIX)

- Register 14H ........................................................................40

7. Functional Description.......................................................41

7.1 System Buffer Management..........................................41

7.1.1 Overview .......................................................................41

7.1.2 Data Structure and Descriptor List .............................41

Figure 7-1…………………………………………….41

7.1.3 Buffer Management: Chain Structure Method..........41

7.1.4 Descriptor List: Buffer Descriptor Format ..................41

7.2 Initialization Procedure....................................................46

7.2.1 Data Buffer Processing Algorithm..............................46

7.2.2 Receive Data Buffer Processing ................................46

Figure 7-2…………………………………………….46

7.2.3 Transmit Data Buffer Processing ...............................47

Figure 7-3…………………………………………….47

7.3 Network Function ............................................................48

7.3.1 Overview .......................................................................48

7.3.2 Receive Process and State Machine ........................48

7.3.3 Transmit Process and State Machine .......................48

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