T

T

a

n

s

c

e

n

d

4

0

P

n

D

E

F

a

s

h

M

o

d

u

e

e

T

T

S

1

2

8

M

~

1

6

G

D

O

M

4

0

V

S

S

Transcend Information Inc.

Ver 1.2

7

True IDE PIO Mode Timing Diagram

Figure 1: True IDE PIO Mode Timing Diagram

Notes:

(1) Device address consists of -CS0, -CS1, and A[02::00]

(2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit)

(3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.

(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is

of IORDY is described in the following three cases:

(4-1) Device never negates IORDY: No wait is generated.

generated.

cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for