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Transcend Information Inc.

Ver 1.2

Host Terminating an Ultra DMA Data-In Burst

The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing

diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters

are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:

Ultra DMA Data Burst Timing Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra

DMA data burst has been transferred.

(b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall

continue to negate -HDMARDY until the Ultra DMA data burst is terminated.

(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two

additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the

host shall be prepared to receive zero, one, two or three additional data words. The additional data

words are a result of cable round trip delay and tRFS timing for the device.

(e) The host shall assert STOP no sooner than tRP after negating -HDMARDY. The host shall not negate

STOP again until after the Ultra DMA data burst is terminated.

(f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not

assert DMARQ again until after the Ultra DMA data burst is terminated.

(g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted

STOP. No data shall be transferred during this assertion. The host shall ignore this transition on

DSTROBE. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated.

(h) The device shall release D[15:00] no later than tAZ after negating DMARQ.

(i) The host shall drive D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step,

the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA

CRC Calculation).

(j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00]

during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification

Ultra DMA CRC Calculation).

(k) The host shall negate -DMACK no sooner than tMLI after the device has asserted DSTROBE and

negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than tDVS

after the host places the result of its CRC calculation on D[15:00].

(l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.

(m) The device shall compare the CRC data received from the host with the results of its own CRC

calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one

command, at the end of the command, the device shall report the first error that occurred (see ATA

specification Ultra DMA CRC Calculation)

(n) While operating in True IDE mode, the device shall release DSTROBE within tIORDYZ after the host

negates -DMACK.

(o) The host shall neither negate STOP nor assert -HDMARDY until at least tACK after the host has

negated -DMACK.

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