M24LR64-R-MB6TSLASH2 datasheet(36/126 Pages) STMICROELECTRONICS

部件名	M24LR64-R-MB6T/2

功能描述	64 Kbit EEPROM with password protection & dual interface: 400kHz I짼C serial bus & ISO 18000-3 mode 1 RF protocol at 13.56MHz

PDF	126 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

36 / 126 page

Initial delivery state

M24LR64-R

36/126

Doc ID 15170 Rev 8

Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

RF device operation

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. Each

sector can be individually read- and/or write-protected using a specific lock or password

command.

Read and Write operations are possible if the addressed block is not protected. During a

Write, the 32 bits of the block are replaced by the new 32-bit value.

The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier

(UID). The UID is compliant with the ISO 15963 description, and its value is used during the

anticollision sequence (Inventory). This block is not accessible by the user and its value is

written by ST on the production line.

The M24LR64-R also includes an AFI register in which the application family identifier is

stored, and a DSFID register in which the data storage family identifier used in the

anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which

the password codes are stored.

M24LR64-R-MB6T/2 数据表(PDF) 36 Page - STMicroelectronics