LTC3633 datasheet(21/28 Pages) LINER

21 / 28 page

LTC3633

3633f

of power loss in the package with corresponding output

load current. Although making this measurement with this

method does violate absolute maximum voltage ratings

on the PGOOD pin, the applied power is so low that there

should be no signiﬁcant risk of damaging the device.

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3633. Check the following in your layout:

1) Do the input capacitors connect to the VIN and PGND

pins as close as possible? These capacitors provide

the AC current to the internal power MOSFETs and their

drivers.

2) The output capacitor, COUT, and inductor L should be

closely connected to minimize loss. The (–) plate of

COUT should be closely connected to both PGND and

the (–) plate of CIN.

3) The resistive divider, (e.g. R1 to R4 in Figure 8) must be

connected between the (+) plate of COUT and a ground

line terminated near SGND. The feedback signal VFB

should be routed away from noisy components and

traces, such as the SW line, and its trace length should

be minimized. In addition, the RT resistor and loop

compensation components should be terminated to

SGND.

4) Keep sensitive components away from the SW pin.

The RT resistor, the compensation components, the

feedback resistors, and the INTVCC bypass capacitor

should all be routed away from the SW trace and the

inductor L.

5) A ground plane is preferred, but if not available, the

signal and power grounds should be segregated with

both connecting to a common, low noise reference point.

The connection to the PGND pin should be made with

a minimal resistance trace from the reference point.

APPLICATIONS INFORMATION

6) Flood all unused areas on all layers with copper in order

to reduce the temperature rise of power components.

These copper areas should be connected to the exposed

backside of the package (PGND).

Refer to Figures 9 and 10 for board layout examples.

Design Example

As a design example, consider using the LTC3633 in an

application with the following speciﬁcations: VIN(MAX)

= 13.2V, VOUT1 = 1.8V, VOUT2 = 3.3V, IOUT(MAX) = 3A,

IOUT(MIN) = 10mA, f = 2MHz, VDROOP ~ (5% • VOUT). The

following discussion will use equations from the previous

sections.

Because efﬁciency is important at both high and low load

current, Burst Mode operation will be utilized.

First, the correct RT resistor value for 2MHz switching fre-

quency must be chosen. Based on the equation discussed

earlier, RT should be 160k; the closest standard value is

162k. RT can be tied to INTVCC if switching frequency

accuracy is not critical.

Next, determine the channel 1 inductor value for about

40% ripple current at maximum VIN:

L1=

1.8V

2MHz • 1.2A

1.8V

13.2V

= 0.64μH

A standard value of 0.68μH should work well here. Solv-

ing the same equation for channel 2 results in a 1μH

inductor.

COUT will be selected based on the charge storage require-

ment. For a VDROOP of 90mV for a 3A load step:

OUT1 ≈

3• ΔIOUT

0 VDROOP

3• (3A)

(2MHz)(90mV)

= 50μF

LTC3633 数据表(PDF) 21 Page - Linear Technology

LTC3633 数据表(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载