PixArt Imaging Inc.

PAS005B

CMOS Image Sensor IC

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PixArt Imaging Inc.

Reg_30[3:0]

Cg_G1[3:0]

R/W

0

Color gain of color G1

Reg_31[3:0]

Cg_G0[3:0]

R/W

0

Color gain of color G0

Reg_32[3:0]

Cg_R[3:0]

R/W

0

Color gain of color R

Reg_33[2:0]

acc1_B[10:8]

R/W

0

2’s complement value for digital calibration of color

B

Reg_34[7:0]

acc1_B[7:0]

R/W

0

2’s complement value for digital calibration of color

G1

Reg_35[2:0]

acc1_G1[10:8]

R/W

0

2’s complement value for digital calibration of color

G1

Reg_36[7:0]

acc1_G1[7:0]

R/W

0

2’s complement value for digital calibration of color

G1

Reg_37[2:0]

acc1_G0[10:8]

R/W

0

2’s complement value for digital calibration of color

G0

Reg_38[7:0]

acc1_G0[7:0]

R/W

0

2’s complement value for digital calibration of color

G0

Reg_39[2:0]

acc1_R[10:8]

R/W

0

2’s complement value for digital calibration of color

R

Reg_40[7:0]

acc1_R[7:0]

R/W

0

2’s complement value for digital calibration of color

R

Reg_41[0]

flag

R/W

0

used to synchronize register update by frame when

fast_i2c is set 0

It will be reset to 0 till the first new frame is readout

after it is set to 1

Reg_42[2]

mode_chg_ena

R/W

1

when it is set to 1, the mode related registers will be

updated only after mode_chg is set to 1

Reg_42[1]

dac_pg_lag

R/W

0

DAC & PGA update delay 1 frame automatically

Reg_42[0]

fast_i2c

R/W

0

fast update of synchronized i2c registers

Reg_43[7]

sfrst_ena

R/W

0

source follower reset enable

Reg_43[6:5]

shr_ext[1:0]

R/W

1

SHR extension CDS_rst1:

00: 9 ck12 01: 14 ck12

10: 19 ck12 11: 24 ck12

Reg_43[4:2]

comp_crv[2:0]

R/W

0

companding curve

Reg_43[1]

Vsync_p

R/W

0

Vsync polarity

Reg_43[0]

Hsync_p

R/W

0

Hsync polarity

Reg_44[7:6]

dacor[1:0]

R/W

0

DAC output range

00: x1/8 01: x1/4

10: x1/2 11: x1

Reg_44[5:0]

offset[5:0]

R/W

1

offset value for ABC

Reg_45[7:0] Threshold_1_by4[7:0]

R/W

25

Threshold_1 divided by 4 for defect compensation

Reg_46[7:0] Threshold_2_by4[7:0]

R/W

13

Threshold_2 divided by 4 for defect compensation

Reg_47[5]

Defect_EnH

R/W

0

0: Defect compensation disable

1: Defect compensation enable

Reg_47[4]

ABC_EnH

R/W

0

ABC enable high

Reg_47[3]

Line_Avg_EnH

R/W

0

Line based digital calibration enable high

Reg_47[2]

Frm_Avg_EnH

R/W

0

Frame based digital calibration enable high

Reg_47[1:0]

Avg_num_index[1:0]

R/W

1

Number of pixels for Frame based digital calibration

00: 4 pixels 01: 8 pixels

10: 16 pixels 11: 32 pixels

Reg_48[6]

DSC_pd

R/W

0

Digital timing(column address, CDS timing) disable