PixArt Imaging Inc.

PAS005B

CMOS Image Sensor IC

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PixArt Imaging Inc.

5. I

PAS005B supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is

1000000 and supports receiving / transmitting speed up to 400kHz.

5.1 I2C bus overview

Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected

to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external

pull-up resistors.

Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop).

Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start

condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please

refer to Fig 5.1.

Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each

byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to

Fig 5.2.

Both the master and slave can transmit and receive data from the bus.

Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock

line when a complete byte was transferred by transmitter. In the case of a master received data from a

slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master

read cycle.

S

Start

Condition

SDA

SCL

P

Stop

Condition

Fig 5.1 Start and Stop Conditions