PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

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8

PixArt Imaging Inc.

V1.2, May. 2002

Fig 4.2

Valid Data

4.2 Data Transfer Format

4.2.1 Master transmits data to slave (write cycle)

§

S : Start

§

A : Acknowledge by slave

§

P : Stop

§

RW : The LSB of 1

RW=1 read cycle, RW=0 write cycle.

§

SUBADDRESS : The address values of PAS202BCA/PAS202BBA internal control registers

(Please refer to PAS202BCA/PAS202BBA register description)

During write cycle, the master generates start condition and then places the 1

slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCA/PAS202BBA) issues

acknowledgment, the master places 2

nd

byte (sub-address) data on SDA line. Again follow the

PAS202BCA/PAS202BBA acknowledgment, the master places the 8 bits data on SDA line and transmit to

PAS202BCA/PAS202BBA

control

register

(address

was

assigned

by

2

nd

byte).

After

PAS202BCA/PAS202BBA issue acknowledgment, the master can generate a stop condition to end of this

write cycle. In the condition of multi-byte write, the PAS202BCA/PAS202BBA sub-address is automatically

increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control

S

SLAVE ID (7 BIT)

RW

A

SUBADDRESS (8 BIT)

A

DATA

P

A

1ST BYTE

2ND BYTE

n BYTEs + A

MSB

LSB=0

A

DATA

DATA

STABLE

DATA

CHANGE

ALLOWED

SDA

SCL