PAS5101CS datasheet(11/19 Pages) PIXART

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PAS5101CS Specification

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PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

v1.0 2005/4/27

4.2. Data Transfer Format

4.2.1. Master transmits data to salve ( write cycle )

S : Start.

A : Acknowledge by salve.

P : Stop.

RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –

Read cycle, RW = 0 – Write cycle.

SUBADDRESS : The address values of PAS5101CS internal control registers. ( Please refer

to PAS5101CS register description )

During write cycle, the master generates start condition and then places the 1st byte data that are

combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS5101CS )

issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the

PAS5101CS acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS5101CS

control register ( address was assigned by 2nd byte ). After PAS5101CS issue acknowledgment, the master

can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the

PAS5101CS sub-address is automatically increment after each DATA byte transferred. The data and A

cycles is repeat until last byte write. Every control registers value inside PAS5101CS can be

programming via this way.

4.2.2. Slave transmits data to master ( read cycle )

The sub-address was taken from previous write cycle.

The sub-address is automatically increment after each byte read.

Am : Acknowledge by master.

Note there is no acknowledgment from master after last byte read.

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